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參數(shù)資料
| 型號： | LTC4258CGW#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/28頁 |
| 文件大小： | 0K |
| 描述： | IC POE 802.3AF QUAD 36-SSOP |
| 標準包裝： | 1,000 |
| 控制器類型： | 以太網(wǎng)供電控制器（POE） |
| 接口： | IEEE 802.3af |
| 電源電壓： | 3 V ~ 4 V |
| 電流 - 電源： | 2.5mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-BSOP（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 36-SSOP |
| 包裝： | 帶卷 (TR) |
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LTC4258
11
4258fb
the register are reserved and will always read as 0. The
Supply Event bits latch high and will remain high until
cleared by reading from address 0Bh.
Supply Event CoR (Address 0Bh): Supply Event Register,
Clear on Read. Read this address to clear the Fault Event
register. Address 0Bh returns the same data as address 0Ah,
and reading address 0Bh clears all bits at both addresses.
Status Registers
Port 1 Status (Address 0Ch): Port 1 Status Register, Read
Only. This register reports the most recent detection and
classification results for port 1. Bits 0-2 report the status
of the most recent detection attempt at the port and bits 4-6
report the status of the most recent classification attempt
at the port. If power is on, these bits report the detection/
classification status present just before power was turned
on. If power is turned off at the port for any reason, all bits
in this register will be cleared. See Table 1 for detection and
classification status bit encoding.
Port 2 Status (Address 0Dh): Port 2 Status Register, Read
Only. See Port 1 Status.
Port 3 Status (Address 0Eh): Port 3 Status Register, Read
Only. See Port 1 Status.
Port 4 Status (Address 0Fh): Port 4 Status Register, Read
Only. See Port 1 Status.
Power Status (Address 10h): Power Status Register, Read
Only. The lower four bits in this register report the switch
on/off state for the corresponding ports. The upper four
bits (the power good bits) indicate that the drop across the
power switch and sense resistor for the corresponding ports
is less than 2V (typ) and power start-up is complete. The
power good bits are latched high and are only cleared when
a port is turned off or the LTC4258 is reset.
Pin Status (Address 11h): External Pin Status, Read Only.
This register reports the real time status of the AUTO
(Pin 35) and AD0-AD3 (Pins 7-10) digital input pins. The
logic state of the AUTO pin appears at bit 0 and the AD0-AD3
pins at bits 2-5. The remaining bits are reserved and will
read as 0. AUTO affects the initial states of some of the
LTC4258 configuration registers at start-up but has no
effect after start-up and can be used as a general purpose
input if desired, as long as it is guaranteed to be in the
appropriate state at start-up.
Configuration Registers
Operating Mode (Address 12h): Operating Mode Configu-
ration, Read/Write. This register contains the mode bits for
each of the four ports in the LTC4258. See Table 1 for mode
bit encoding. At power-up, all bits in this register will be set
to the logic state of the AUTO pin (Pin 35). See Operating
Modes in the Applications Information section.
Disconnect Enable (Address 13h): Disconnect Enable
Register, Read/Write. The lower four bits of this register
enable or disable DC disconnect detection circuitry at the
corresponding port. If the DC Discon Enable bit is set the
port circuitry will turn off power if the current draw at the
port falls below IMINformorethantDIS.IMINisequaltoVMIN/
RS, where RS is the sense resistor and should be 0.5 for
IEEE 802.3af compliance. If the bit is clear the port will not
remove power due to low current.
Detect/Class Enable (Address 14h): Detection and Clas-
sification Enable, Read/Write. The lower four bits of this reg-
ister enable the detection circuitry at the corresponding port
if that port is in Auto or Semiauto mode. The upper four bits
enable the classification circuitry at the corresponding port
if that port is in Auto or Semiauto mode. In manual mode,
setting a bit in this register will cause the LTC4258 to per-
form one classification or detection cycle on the corre-
sponding port. Writing to the Detect/Class Restart PB (18h)
has the same effect without disturbing the Detect/Class
Enable bits for other ports.
Timing Config (Address 16h):Global Timing Configuration,
Read/Write. Bits 0-1 program tDIS, the time duration before
a port is automatically tuned off after the PD is removed.
Bits 2-3 program tICUT, the time during which a port’s
current can exceed ICUT without it being turned off. If the
current is still above ICUT after tICUT, the LTC4258 will in-
dicate a tICUT fault and turn the port off. Bits 4-5 program
tSTART, the time duration before an overcurrent condition
during port power-on is considered a tSTART fault and the
port is turned off. Note that using the tICUT and tSTART times
other than the default is not compliant with IEEE 802.3af
and may double or quadruple the energy dissipated by the
external MOSFETs during fault conditions. Bits 6-7 are re-
served and should be read/written as 0. See Electrical Char-
acteristics for timer bit encoding. Also see the Applications
Information for descriptions of tSTART,tICUT andDCdiscon-
nect timing.
REGISTER FU CTIO S
U
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