- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1934 > LTC4258CGW#TRPBF (Linear Technology)IC POE 802.3AF QUAD 36-SSOP PDF資料下載
參數(shù)資料
| 型號(hào)： | LTC4258CGW#TRPBF |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 26/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC POE 802.3AF QUAD 36-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 控制器類型： | 以太網(wǎng)供電控制器（POE） |
| 接口： | IEEE 802.3af |
| 電源電壓： | 3 V ~ 4 V |
| 電流 - 電源： | 2.5mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-BSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 36-SSOP |
| 包裝： | 帶卷 (TR) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)當(dāng)前第26頁(yè)第27頁(yè)第28頁(yè)
LTC4258
7
4258fb
Figure 8. Reading the Interrupt Register (Short Form)
Figure 9. Reading from Alert Response Address
SCL
SDA
4258 F08
01
0
AD3 AD2 AD1 AD0
D7
D6
D5
D4
D3
D2
D1
D0
R/W ACK
ACK
START BY
MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE
STOP BY
MASTER
SCL
SDA
4258 F09
00
1
0
AD3
0
1
AD2 AD1 AD0
R/W ACK
ACK
1
START BY
MASTER
ACK BY
SLAVE
NO ACK BY
MASTER
FRAME 1
ALERT RESPONSE ADDRESS BYTE
FRAME 2
SERIAL BUS ADDRESS BYTE
STOP BY
MASTER
TI I G DIAGRA S
W
U
W
UU
U
PI FU CTIO S
RESET (Pin 1): Chip Reset, Active Low. When the RESET
pin is low, the LTC4258 is held inactive with all ports off
and all internal registers reset to their power-up states.
When RESET is pulled high, the LTC4258 begins normal
operation. RESET can be connected to an external capaci-
tor or RC network to provide a power turn-on delay.
Internal filtering of the RESET pin prevents glitches less
than 1
s wide from resetting the LTC4258. Pull RESET
high with
≤10k or tie to VDD.
BYP (Pin 2): Bypass Output. The BYP pin is used to
connect the internally generated – 20V supply to an exter-
nal 0.1
F bypass capacitor. Use a 100V rated 0.1F, X7R
capacitor. Do not connect the BYP pin to any other external
circuitry.
INT (Pin 3): Interrupt Output, Open Drain. INT will pull low
when any one of several events occur in the LTC4258. It
will return to a high impedance state when bits 6 or 7 are
set in the Reset PB register (1Ah). The INT signal can be
used to generate an interrupt to the host processor,
eliminating the need for continuous software polling.
Individual INT events can be disabled using the Int Mask
register (01h). See Register Functions and Applications
Information for more information. The INT pin is only
updated between I2C transactions.
SCL (Pin 4): Serial Clock Input. High impedance clock
input for the I2C serial interface bus. The SCL pin should
be connected directly to the I2C SCL bus line.
SDAOUT (Pin 5): Serial Data Output, Open Drain Data
Output for the I2C Serial Interface Bus. The LTC4258 uses
two pins to implement the bidirectional SDA function to
simplify optoisolation of the I2C bus. To implement a stan-
dard bidirectional SDA pin, tie SDAOUT and SDAIN together.
See Applications Information for more information.
SDAIN (Pin 6): Serial Data Input. High impedance data input
for the I2C serial interface bus. The LTC4258 uses two pins
to implement the bidirectional SDA function to simplify
optoisolation of the I2C bus. To implement a standard
bidirectional SDA pin, tie SDAOUT and SDAIN together.
See Applications Information for more information.
AD3 (Pin 7): Address Bit 3. Tie the address pins high or low
to set the I2C serial address to which the LTC4258 re-
sponds. This address will be (010A3A2A1A0)b. Pull AD3
high or low with
≤10k or tie to VDD or DGND.
AD2 (Pin 8): Address Bit 2. See AD3.
AD1 (Pin 9): Address Bit 1. See AD3.
AD0 (Pin 10): Address Bit 0. See AD3.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC4259ACGW#TR | IC CTRLR POE QUAD AC DISC 36SSOP |
| LTC4264IDE#TRPBF | IC CNTRLR PD INTERFACE 12-DFN |
| LTC4266IGW#PBF | IC CTRLR IEEE 802.3AT 36-SSOP |
| LTC4267IDHC#TRPBF | IC POE 802.3AF INTERFACE 16-DFN |
| LTC4278IDKD#TRPBF | IC PD IEEE 802.3AT 25.5W 32-DFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC4259A | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Power over Ethernet IEEE 802.3af PD Interface with Integrated Switching Regulator |
| LTC4259A-1 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Synchronous No-Opto Flyback Controller |
| LTC4259ACGW | 功能描述:IC CTRLR POE QUAD AC DISC 36SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:2,450 系列:- 控制器類型:SPI 總線至 I²C 總線橋接 接口:I²C，串行，SPI 電源電壓:2.4 V ~ 3.6 V 電流 - 電源:11mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-HVQFN（4x4） 包裝:托盤 配用:568-3511-ND - DEMO BOARD SPI TO I2C 其它名稱:935286452157SC18IS600IBSSC18IS600IBS-ND |
| LTC4259ACGW#PBF | 功能描述:IC CTRLR POE QUAD AC DISC 36SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:2,450 系列:- 控制器類型:SPI 總線至 I²C 總線橋接 接口:I²C，串行，SPI 電源電壓:2.4 V ~ 3.6 V 電流 - 電源:11mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-HVQFN（4x4） 包裝:托盤 配用:568-3511-ND - DEMO BOARD SPI TO I2C 其它名稱:935286452157SC18IS600IBSSC18IS600IBS-ND |
| LTC4259ACGW#TR | 功能描述:IC CTRLR POE QUAD AC DISC 36SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:2,450 系列:- 控制器類型:SPI 總線至 I²C 總線橋接 接口:I²C，串行，SPI 電源電壓:2.4 V ~ 3.6 V 電流 - 電源:11mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-HVQFN（4x4） 包裝:托盤 配用:568-3511-ND - DEMO BOARD SPI TO I2C 其它名稱:935286452157SC18IS600IBSSC18IS600IBS-ND |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。