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參數(shù)資料
| 型號： | LTC3827IG-1 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 3 A DUAL SWITCHING CONTROLLER, 650 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | 5.30 MM, PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 13/32頁 |
| 文件大?。?/td> | 448K |
| 代理商： | LTC3827IG-1 |
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LTC3827-1
20
38271fe
APPLICATIONS INFORMATION
Phase-Locked Loop and Frequency Synchronization
The LTC3827-1 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the top MOSFET
of controller 1 to be locked to the rising edge of an external
clock signal applied to the PLLIN/MODE pin. The turn-on
of controller 2’s top MOSFET is thus 180 degrees out of
phase with the external clock. The phase detector is an
edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the external lter
network connected to the PLLLPF pin. The relationship
between the voltage on the PLLLPF pin and operating
frequency, when there is a clock signal applied to PLLIN/
MODE, is shown in Figure 9 and specied in the Electrical
Characteristics table. Note that the LTC3827-1 can only
be synchronized to an external clock whose frequency is
within range of the LTC3827-1’s internal VCO, which is
nominally 115kHz to 800kHz. This is guaranteed to be
between 140kHz and 650kHz. A simplied block diagram
is shown in Figure 10.
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than fOSC, current is sunk continuously, pulling down
the PLLLPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLLPF pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the lter capacitor, CLP, holds the voltage.
The loop lter components, CLP and RLP, smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The lter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP = 10k and CLP is 2200pF to
0.01μF.
Typically, the external clock (on PLLIN/MODE pin) input high
threshold is 1.6V, while the input low threshold is 1.2V.
Table 2 summarizes the different states in which the
PLLLPF pin can be used.
Table 2
PLLLPF PIN
PLLIN/MODE PIN
FREQUENCY
0V
DC Voltage
250kHz
Floating
DC Voltage
400kHz
INTVCC
DC Voltage
530kHz
RC Loop Filter
Clock Signal
Phase-Locked to External Clock
Figure 10. Phase-Locked Loop Block Diagram
DIGITAL
PHASE/
FREQUENCY
DETECTOR
OSCILLATOR
2.4V
RLP
CLP
3827 F10
PLLLPF
EXTERNAL
OSCILLATOR
PLLIN/
MODE
Figure 9. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
PLLLPF PIN VOLTAGE (V)
0
FREQUENCY
(kHz)
0.5
1
1.5
2
3827 F09
2.5
0
100
300
400
500
900
800
700
200
600
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| LTC3827IG-1#PBF | 功能描述:IC REG CTRLR BUCK PWM CM 28-SSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:PolyPhase® 標(biāo)準(zhǔn)包裝:4,500 系列:PowerWise® PWM 型:控制器 輸出數(shù):1 頻率 - 最大:1MHz 占空比:95% 電源電壓:2.8 V ~ 5.5 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 125°C 封裝/外殼:6-WDFN 裸露焊盤 包裝:帶卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名稱:LM1771SSDX |
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