參數(shù)資料
型號(hào): LTC3788IGN-1#PBF
廠(chǎng)商: LINEAR TECHNOLOGY CORP
元件分類(lèi): 穩(wěn)壓器
英文描述: DUAL SWITCHING CONTROLLER, 900 kHz SWITCHING FREQ-MAX, PDSO28
封裝: 0.150 INCH, LEAD FREE, PLASTIC, SSOP-28
文件頁(yè)數(shù): 15/30頁(yè)
文件大小: 384K
代理商: LTC3788IGN-1#PBF
LTC3788-1
22
37881fb
applicaTions inForMaTion
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is complete
and the particular output capacitor type and value have
been determined. The output capacitors must be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1s to 10s will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop.
Placing a power MOSFET and load resistor directly across
the output capacitor and driving the gate with an ap-
propriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the ITH pin signal which is
in the feedback loop and is the filtered and compensated
control loop response.
The gain of the loop will be increased by increasing RC
and the bandwidth of the loop will be increased by de-
creasing CC. If RC is increased by the same factor that CC
is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loopsystemandwilldemonstratetheactualoverall
supply performance.
A second, more severe transient is caused by switching
in loads with large (>1F) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited to
approximately 25 CLOAD. Thus, a 10F capacitor would
require a 250s rise time, limiting the charging current
to about 200mA.
Design Example
As a design example for one channel, assume VIN =
12V(nominal), VIN = 22V (max), VOUT = 24V, IOUT(MAX) =
4A, VSENSE(MAX) = 75mV, and f = 350kHz.
The inductance value is chosen first based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLLPF
pin to GND, generating 350kHz operation. The minimum
inductance for 30% ripple current is:
IL =
VIN
f L
1
VIN
VOUT
A 6.8H inductor will produce a 30% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 9.25A.
The RSENSE resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
RSENSE
75mV
9.25A
= 0.008
Choosing 1% resistors: RA = 5k and RB = 95.3k yields an
output voltage of 24.072V.
The power dissipation on the top side MOSFET can
be easily estimated. Choosing a Vishay Si7848BDP
MOSFET results in: RDS(ON) = 0.012Ω, CMILLER = 150pF.
At maximum input voltage with T(estimated) = 50°C:
PMAIN =
(24V
12V) 24V
(12V)2
(4A)2
1
+(0.005)(50°C 25°C)
[
]0.008
+ (1.7)(24V)3
4A
12V
(150pF)(350kHz)
= 0.7W
COUT is chosen to filter the square current in the output.
The maximum output current peak is:
IOUT(PEAK) = 4 1+
31%
2
=
4.62A
A low ESR (5m) capacitor is suggested. This capacitor
will limit output voltage ripple to 23.1mV (assuming ESR
dominate ripple).
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