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參數(shù)資料
| 型號： | LTC3776 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 16-Bit Buffer/Driver With 3-State Outputs 48-TVSOP -40 to 85 |
| 中文描述： | 雙2相，無檢測電阻同步控制器用于DDR / QDR存儲器終端 |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 429K |
| 代理商： | LTC3776 |
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6
LTC3776
3776f
PIU
I
TH1
/I
TH2
(Pins 1, 8/ Pins 4, 11):
Current Threshold and
Error Amplifier Compensation Point. Nominal operating
range on these pins is from 0.7V to 2V. The voltage on
these pins determines the threshold of the main current
comparator.
PLLLPF (Pin 3/Pin 6):
Frequency Set/PLL Lowpass Filter.
When synchronizing to an external clock, this pin serves
as the lowpass filter point for the phase-locked loop. Nor-
mally a series RC is connected between this pin and ground.
When SYNC/SSEN is tied to GND, this pin serves as the fre-
quency select input. Tying this pin to GND selects 300kHz
operation; tying this pin to V
IN
selects 750kHz operation.
Floating this pin selects 550kHz operation. When SYNC/
SSEN is tied to V
IN
to enable spread spectrum operation,
a capacitor (1nF to 4.7nF) should be connected from this
pin to SGND to filter and smooth the changes in frequency
of the LTC3776’s internal oscillator.
SGND (Pin 4/Pin 7):
Small-Signal Ground. This pin serves
as the ground connection for most internal circuits.
V
IN
(Pin 5/Pin 8):
Chip Signal Power Supply. This pin
powers the entire chip except for the gate drivers. Externally
filtering this pin with a lowpass RC network (e.g.,
R = 10
, C = 1
μ
F) is suggested to minimize noise pickup,
especially in high load current applications.
V
REF
(Pin 6/Pin 9):
Reference voltage input for channel 2.
(UF/GN Package)
The positive input of the error amplifier for channel 2 senses
one half of the voltage on this pin through an internal
resistor divider.
PGOOD (Pin 9/Pin 12):
Power Good Output Voltage Moni-
tor Open-Drain Logic Output. This pin is pulled to ground
when the voltage on either feedback pin (V
FB1
, V
FB2
) is not
within
±
13.3% of its nominal set point.
PGND (Pins 12, 16, 20, 25/ Pins 15, 19, 23):
Power
Ground. These pins serve as the ground connection for the
gate drivers and the negative input to the reverse current
comparators. The Exposed Pad (UF package) must be
soldered to PCB ground.
RUN/SS (Pin 14/Pin 17):
Run Control Input and Optional
External Soft-Start Input. Forcing this pin below 0.65V shuts
down the chip (both channels). Driving this pin to V
IN
or
releasing this pin enables the chip, using the chip’s inter-
nal soft-start. An external soft-start can be programmed by
connecting a capacitor between this pin and ground.
TG1/TG2 (Pins 17, 15/Pins 20, 18):
Top (PMOS) Gate Drive
Output. These pins drive the gates of the external P-channel
MOSFETs. These pins have an output swing from PGND to
SENSE
+
.
SYNC/SSEN (Pin 18/Pin 21):
Synchronization Input and
Spread Spectrum Modulation Enable Input. To synchronize
the LTC3776’s switching frequency to an external clock
Shutdown Quiescent Current
vs Input Voltage
INPUT VOLTAGE (V)
2
0
S
μ
A
2
6
8
10
20
14
4
6
7
3736 G17
4
16
18
12
3
5
8
9
10
RUN/SS = 0V
RUN/SS Start-Up Current
vs Input Voltage
INPUT VOLTAGE (V)
2
R
μ
A
0.5
0.6
0.7
10
3736 G18
0.4
0.3
0
0.1
4
6
8
3
5
7
9
0.2
0.9
0.8
RUN/SS = 0V
TYPICAL PERFOR U
T
A
= 25
°
C unless otherwise noted.
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| LTC3776EGN | 制造商:Linear Technology 功能描述:DC DC Cntrlr Dual-OUT Sync Step Down 2.75V to 9.8V Input 24-Pin SSOP N |
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| LTC3776EGNPBF | 制造商:Linear Technology 功能描述:DC-DC Controller Dual Step-Down SSOP24 |
| LTC3776EUF | 制造商:Linear Technology 功能描述:DC DC Cntrlr Dual-OUT Sync Step Down 2.75V to 9.8V Input 24-Pin QFN EP |
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