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參數(shù)資料
| 型號： | LTC3766MPUFD#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 316 kHz SWITCHING FREQ-MAX, PQCC28 |
| 封裝： | 4 X 5 MM, LEAD FREE, PLASTIC, MO-220, QFN-28 |
| 文件頁數(shù)： | 27/60頁 |
| 文件大?。?/td> | 607K |
| 代理商： | LTC3766MPUFD#TRPBF |
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LTC3766
33
3766f
APPLICATIONS INFORMATION
In addition to being set to minimize the dead time between
SG falling and PG rising, the FG rising delay should also
be adjusted to ensure that the drain of the forward switch
(SWB) is close to 0V when the switch is turned on, which
minimizesswitchingloss.WhentheLTC3765activeclamp
switch turns off, the drain voltage of the primary switch
(SWP) decreases linearly from VIN/(1 – D) to VIN, where D
is the duty cycle. On the secondary side of the transformer,
SWB ramps from VOUT/(1 – D) to 0V. Switching power
loss is minimized when FG and PG MOSFETs are switched
with minimal drain-to-source voltage across them. The FG
and PG rising delays should be adjusted to ensure that
the SWB and SWP nodes are at their minimums when the
switches are turned on.
Keep in mind the following set of relationships when set-
ting the delays (refer to the Timing Diagram and Figure 1):
1. The forward gate (FG) always turns on with make-
before-break timing relative to the synchronous gate
(SG). This ensures that negative inductor current does
notcreateexcessivevoltageonthesynchronousswitch
drain.
2. Shoot-through is caused when the synchronous gate
(SG) and the LTC3765 primary gate (PG) are simulta-
neously high, or when the forward gate (FG) is high
and the LTC3765 active gate (AG) is low. The leakage
inductance of the main transformer will prevent signifi-
cant power loss due to shoot-through for a few tens
of nanoseconds; however, if the PG and SG or FG and
AG gates are on simultaneously for a longer period of
time, the shoot-through will cause power loss, exces-
sive heat, and potentially rapid part displacement.
3. The primary side turn-off of either AG or PG should
occur before FG and SG switch, and the primary-side
turn-on should occur after FG and SG switch. For ex-
ample, on a particular cycle, AG goes high first (turning
the PMOS off), then FG goes high, then SG goes low,
then PG goes high. On the PG turn-off edge, PG goes
low first, then FG goes low and SG goes high, then AG
goes low (turning the PMOS on).
Delay Resistor Selection: PG Turn-Off Transition
In general, the PG turn-off delays are relatively simpler
to set and less critical than the PG turn-on delays. At the
end of the PWM on-time, the LTC3766 will assert a falling
edge on the PT+ pin, which in turn causes the LTC3765 to
immediately turn off the PG MOSFET. After a fixed 180ns
delay, the LTC3765 will then turn on the AG MOSFET.
Consequently, the only delay adjustment to be made for
this transition is on the secondary side using the SGD pin
of the LTC3766. This pin is used to set the delay from PT+
falling to FG falling/SG rising, which must occur after PG
turn-off and before AG turn-on.
The first consideration in setting the SGD delay is to
reduce the dead time between PG and SG, during which
the body diode of the synchronous MOSFET is carrying
the load current. After PG turn-off, the SW node on the
secondary side will rapidly fall until being clamped by the
body diode of the SG MOSFET. The objective is to turn on
the SG MOSFET as the SW node crosses through 0V. The
LTC3766 makes this easy to achieve by directly sensing
the SW node and inhibiting SG turn-on until SW has fallen
through0.5V.Inotherwords,minimumdeadtimebetween
PG and SG can be achieved by setting the SGD delay to any
value less than or equal to the delay time from PT+ falling to
SW falling through 0V. In general, this delay time is in the
range of 50ns to 100ns. The resistor from SGD to ground
that gives a particular delay tSGD can be computed using:
RSGD = tSGD –12ns
(
) 1k
4.3ns
A 10k resistor from SGD to ground sets the FG falling/SG
rising delay to approximately 50ns, which is generally a
good starting point. To prevent damaging cross conduc-
tion between the FG and AG MOSFETs, do not set the
SGD delay to be longer than the 180ns fixed turn-on
delay of the AG MOSFET. Always start low when setting
the SGD delay. This is safe because of the adaptive limit
that inhibits premature SG turn-on.
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