參數(shù)資料
型號(hào): LTC3766IGN#PBF
廠商: LINEAR TECHNOLOGY CORP
元件分類(lèi): 穩(wěn)壓器
英文描述: SWITCHING CONTROLLER, 316 kHz SWITCHING FREQ-MAX, PDSO28
封裝: 0.150 INCH, LEAD FREE, PLASTIC, SSOP-28
文件頁(yè)數(shù): 40/60頁(yè)
文件大?。?/td> 607K
代理商: LTC3766IGN#PBF
LTC3766
45
3766f
APPLICATIONS INFORMATION
The SG overcurrent trip should normally be targeted at
twice the maximum VDS of the SG MOSFET during normal
operation. This can be estimated using:
VOC =
RDS(MAX)VOUT
fSWL
1–
VOUT
VIN(MAX)
NP
NS
where RDS(MAX) is the maximum RDS(ON) of the SG
MOSFET over temperature. This equation allows for twice
the reverse SG current that would normally occur due to
the inductor current ripple at no load. The % error in the
SG overcurrent trip can be estimated using:
VOC =
100
VOC
IREVRSW
15
2
+
VREV
15
2
If the above error is greater than 30%, then the VOCthresh-
old may need to be increased accordingly. To ensure that
the inductor doesn’t saturate prior to the SG overcurrent
trip,theinductorshouldhaveasaturationcurrentsuchthat:
ILSAT >
VOC(MAX)
RDS(MIN)
where VOC(MAX) is the maximum overcurrent trip based
on the above error and RDS(MIN) is the minimum RDS(ON)
of the SG MOSFET over temperature.
While the circuit of Figure 30 can be used whenever the
SW node plateau voltage is 40V or less, care must be
taken to limit the current into the 50V clamp on the SW
pin due to overshoot and ringing. Figure 31 illustrates a
typical SW node waveform.
+
SGOC
3766 F32
LTC3766
SW
R3
R2
MAIN
XFMR
VOUT
VSW
SG
VDS(OC)
+
SG
MOSFET
GND
50V
IREV =
LV: 103A
HV: 42A
VREV =
LV: 73mV
HV: 148mV
C
R1
Figure 32. SG Overcurrent for High VOUT Applications
The overshoot and ringing on the SW node is due to the
leakage inductance of main transformer, and it is worse
at full load and maximum VIN. The peak SW node voltage
(VSW(PK)) also depends heavily on the gate drive timing
as well as the RC snubber that is typically used on the SW
node. See Delay Resistor Selection: PG Turn-On Transition
and RC Snubber sections for details. Make sure that the
peak SW node voltage does not cause more than 0.2A to
flow into the SW pin:
VSW(PK) –50V
RSW
< 0.2A
The above condition is normally satisfied with reasonable
values for RSW and the use of an RC snubber to limit
VSW(PK).
In applications where the SW node plateau voltage is
greater than 40V, it is necessary to add a divider as shown
in Figure 32.
+
SGOC
3766 F30
LTC3766
SW
RSW
MAIN
XFMR
VOUT
VSW
SG
VOC
+
SG
MOSFET
GND
50V
IREV =
LV: 103A
HV: 42A
VREV =
LV: 73mV
HV: 148mV
C
Figure 30. SG Overcurrent for Low VOUT Applications
0V
VSW(PK)
PG
SW NODE
0V
3766 F31
VIN
NS
NP
Figure 31. Typical SW Node Waveform
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