參數(shù)資料
型號(hào)： LTC3766EUFD#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類(lèi)： 穩(wěn)壓器
英文描述： SWITCHING CONTROLLER, 316 kHz SWITCHING FREQ-MAX, PQCC28
封裝： 4 X 5 MM, LEAD FREE, PLASTIC, MO-220, QFN-28
文件頁(yè)數(shù)： 39/60頁(yè)
文件大小： 607K
代理商： LTC3766EUFD#PBF
LTC3766
44
3766f
APPLICATIONS INFORMATION
associated with the dominant pole. A high frequency pole
is also added to reduce noise and provide attenuation of
the output voltage ripple. Note that significant gain at the
switching frequency in this compensation network can
cause instabilities.
The network of Figure 29 has a DC gain of:
ADC2 =
R2
+R3
gmREA
where REA = 5MΩ is the output resistance of the error
amplifier and gm = 2.7mS is the transconductance. The
low frequency pole and zero are given by:
fP1=
1
2
πREAC3
and fZ1=
1
2
πR1C1
and the high frequency pole is given by:
fP2 =
1
2
πR1C2
A good target for the 0dB crossover frequency of the
voltage loop is between one-tenth and one-fifth of the
switching frequency and a phase margin of 60° or more.
Note that the zero produced by the ESR of the output
capacitor helps to stabilize the loop by providing positive
phase shift at frequencies near crossover. This tends to
cancel the negative phase shift associated with the high
frequency current loop poles. However, if the output
capacitor is purely ceramic, the ESR zero may be at too
high a frequency to contribute phase lead to the overall
loop response. In this case, it can be helpful to add an
optional phase lead capacitor C3 as shown in Figure 29,
which generates a zero at a frequency of:
fZ2 =
1
2
πR3C3
This zero should be placed near the crossover frequency
to provide additional phase boost.
When optimizing the voltage loop, bear in mind that the
large signal step response may be limited by factors other
than the crossover frequency. At low input voltage, for
example, the maximum duty cycle limit of 79% will impair
the ability of the loop to respond to a sudden increase in
load. Also, in responding to a very large load step (e.g.,
zero to full load) the loop may demand duty cycles that
cause the main transformer to saturate. Hard saturation
is prevented if current in sensed on the primary side or if
the volt-second clamp is used, but the large signal step
response will be limited by the available excess volt-
seconds in the main transformer.
Setting the SG Reverse Overcurrent
The LTC3766 has been carefully designed to turn off the
SG MOSFET as needed to prevent an overcurrent during
start-up, shutdown and normal operation. Nevertheless,
the LTC3766 also contains a user-adjustable SG reverse-
overcurrent protection circuit as an added protection
feature. This feature is also useful in special applications
where it may be advantageous to limit the SG reverse
current to a particular value. SG reverse overcurrent is
implemented by monitoring the voltage on the SW pin
when SG is high, and terminating the SG on-time for the
duration of the switching cycle if the SW voltage exceeds
an internal threshold. If the LTC3766 is operating at zero
duty cycle when the SG overcurrent occurs, then the FG
MOSFET is forced on prior to SG turn-off to re-route cur-
rent to the primary and prevent avalanche from occurring.
If not adjusted, the internal SG overcurrent threshold has
been set high enough so that it should not interfere with
the operation of normal applications. Be careful to make
Kelvin connections from SW and GND to the drain and
source of the SG MOSFET.
In addition to a fixed internal threshold on the SW pin, a
currentissourcedfromtheSWpinsothataresistorcanbe
addedtodecreasetheovercurrentthresholdifdesired.Both
the SW pin threshold and the adjust current are changed
depending on whether the LTC3766 is operating in HV or
LV mode, so as to account for the higher on-resistance
of high voltage MOSFETs. In applications where the SW
node plateau voltage is 40V or less (VIN NS/NP ≤ 40),
a single resistor can be used to set the SG overcurrent
threshold (Figure 30). The resulting overcurrent VDS on
the SG MOSFET is given by:
VOC = VREV – IREVRSW
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