參數(shù)資料
型號(hào)： LTC3765IMSE#TRPBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 電源管理
英文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16
封裝： LEAD FREE, PLASTIC, MSOP-16
文件頁(yè)數(shù)： 14/24頁(yè)
文件大?。?/td> 265K
代理商： LTC3765IMSE#TRPBF
LTC3765
21
3765f
APPLICATIONS INFORMATION
In addition to voltage rating, another design constraint
on CCLAMP occurs because of the resonance between the
magnetizing inductance of the main transformer with the
clamp capacitor. The magnetizing inductance LMAG and
CCLAMP form a high-Q resonant system that results in a
sinusoidal ripple on the capacitor voltage. To avoid the
problems associated with this resonance, always use
an RC snubber in parallel with the clamp capacitor as
shown in Figures 7a and 7b. Choose values for the clamp
capacitor and the snubber components according to the
following equations, where fSW is the frequency set by
the LTC3766 FS pin:
CCLAMP =
1
2LMAG
4
2
π fSW
2
CSN = 6CCLAMP
RSN =
1
1–
VOUT
VIN(MIN)
NP
NS
LMAG
CCLAMP
Becarefultoaccountfortheeffectofvoltagecoefficientfor
both CSN and CCLAMP to ensure that the above relationship
is maintained. In addition to dampening the resonance of
the active clamp, the RC snubber also minimizes the peak
voltage stress seen by the primary-side MOSFETs and
reduces the effect of this LC resonance on the closed-loop
transient response.
Setting the Gate Drive Delay
The active clamp gate driver (AG) and the primary switch
gate driver (PG) switch “in-phase,” with a programmable
overlap time set by the DELAY pin. The PG falling to AG
falling delay (tDAG) is fixed at 180ns since the timing of
this edge has little impact on efficiency. The AG rising to
PG rising delay (tDPG) is critical for optimizing efficiency
and must be set in conjunction with the LTC3766 forward
gate and synchronous gate delays. Refer to the LTC3766
datasheetfortheproceduretodeterminetheoptimaldelay
times for a particular application. The primary gate delay
time is set by a resistor from the DELAY pin to ground,
according to the following equation:
RDELAY = tDPG – 45ns
(
) 1k
9.5ns
In a system where the active clamp is not desired, for
example in a forward converter using resonant reset, this
delay can be set to a minimum by grounding the delay pin.
Maximum Duty Cycle
During the delay time between AG rising and PG rising,
power is not transferred from the input supply to the
output supply. In most forward converter systems, the
maximum on-time is artificially limited by the delay, which
then drives a trade-off between the optimal delay time
and the maximum achievable duty cycle. The LTC3765
and LTC3766 implement a unique system in which the
PG and FG rising delays are reduced as the demanded
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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LTC3765MPMSE#TRPBF 功能描述:IC CONTROLLER GATE DR 16MSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:Direct Flux Limit™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 應(yīng)用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR)
LTC3766EGN#PBF 功能描述:IC CONTROLLER SYNCH 28-SSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:Direct Flux Limit™, PolyPhase® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 應(yīng)用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR)
LTC3766EGN#TRPBF 功能描述:IC CONTROLLER SYNCH 28SSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:Direct Flux Limit™, PolyPhase® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 應(yīng)用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR)
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