參數(shù)資料
型號: LTC3713EG
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: Low Input Voltage, High Power, No RSENSE Synchronous Buck DC/DC Controller
中文描述: 2 A SWITCHING CONTROLLER, 1900 kHz SWITCHING FREQ-MAX, PDSO24
封裝: PLASTIC, SSOP-24
文件頁數(shù): 9/24頁
文件大?。?/td> 325K
代理商: LTC3713EG
9
LTC3713
3713fa
Main Control Loop
The LTC3713 is a current mode controller for DC/DC
step-down converters designed to operate from low input
voltages. It incorporates a boost converter with a buck
regulator.
Buck Regulator Operation
In normal operation, the top MOSFET is turned on for a
fixed interval determined by a one-shot timer OST. When
the top MOSFET is turned off, the bottom MOSFET is
turned on until the current comparator I
CMP
trips, restart-
ing the one-shot timer and initiating the next cycle. Induc-
tor current is determined by sensing the voltage between
the SENSE
+
and SENSE
pins using the bottom MOSFET
on-resistance . The voltage on the I
TH
pin sets the com-
parator threshold corresponding to inductor valley cur-
rent. The error amplifier EA adjusts this voltage by com-
paring the feedback signal V
FB1
from the output voltage
with an internal 0.8V reference. If the load current in-
creases, it causes a drop in the feedback voltage relative to
the reference. The I
TH
voltage then rises until the average
inductor current again matches the load current.
At low load currents, the inductor current can drop to zero
and become negative. This is detected by current reversal
comparator I
REV
which then shuts off M2, resulting in
discontinuous operation. Both switches will remain off
with the output capacitor supplying the load current until
the I
TH
voltage rises above the zero current level (0.8V) to
initiate another cycle. Discontinuous mode operation is
disabled by comparator F when the FCB pin is brought
below 0.8V, forcing continuous synchronous operation.
The operating frequency is determined implicitly by the
top MOSFET on-time and the duty cycle required to
maintain regulation. The one-shot timer generates an on-
time that is proportional to the ideal duty cycle, thus
holding frequency approximately constant with changes
in V
IN
. The nominal frequency can be adjusted with an
external resistor R
ON
.
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a
±
7.5% window around the regulation point.
Furthermore, in an overvoltage condition, M1 is turned off
OPERATIOU
and M2 is turned on and held on until the overvoltage
condition clears.
Foldback current limiting is provided if the output is
shorted to ground. As V
FB1
drops, the buffered current
threshold voltage I
THB
is pulled down by clamp Q3 to a 1V
level set by Q4 and Q6. This reduces the inductor valley
current level to one sixth of its maximum value as V
FB1
approaches 0V.
Pulling the RUN/SS pin low forces the controller into its
shutdown state, turning off both M1 and M2. Releasing
the pin allows an internal 1.2
μ
A current source to charge
up an external soft-start capacitor C
SS
. When this voltage
reaches 1.5V, the controller turns on and begins switch-
ing, but with the I
TH
voltage clamped at approximately
0.6V below the RUN/SS voltage. As C
SS
continues to
charge, the soft-start current limit is removed.
INTV
CC
Power
Power for the top and bottom MOSFET drivers and most
of the internal controller circuitry is derived from the
INTV
CC
pin. The top MOSFET driver is powered from a
floating bootstrap capacitor C
B
. This capacitor is re-
charged from INTV
CC
through an external Schottky diode
D
B
when the top MOSFET is turned off.
Boost Regulator Operation
The 5V power source for INTV
CC
can be provided by a
current mode, internally compensated fixed frequency
step-up switching regulator that has been incorporated
into the LTC3713.
Operation can be best understood by referring to the
Functional Diagrams. Q1 and Q2 form a bandgap refer-
ence core whose loop is closed around the output of the
regulator. The voltage drop across R5 and R6 is low
enough such that Q1 and Q2 do not saturate, even when
V
IN2
is 1V. When there is no load, V
FB2
rises slightly above
1.23V, causing V
C
(the error amplifier’s output) to de-
crease. Comparator A2’s output stays high, keeping switch
Q3 in the off state. As increased output loading causes the
V
FB2
voltage to decrease, A1’s output increases. Switch
current is regulated directly on a cycle-by-cycle basis by
the V
C
node. The flip-flop is set at the beginning of each
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