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| 型號： | LTC3589IUJ-1#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING REGULATOR, 2600 kHz SWITCHING FREQ-MAX, PQCC40 |
| 封裝： | 6 X 6 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, QFN-40 |
| 文件頁數(shù)： | 28/46頁 |
| 文件大小： | 570K |
| 代理商： | LTC3589IUJ-1#TRPBF |
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LTC3589/LTC3589-1
34
3589fc
Figure 19. LTC3589/LTC3589-1 I2C Serial Port Multiple Write Pattern
1
2
34567
8
9
0
1
0
1
0
0 WR
S7 S6 S5 S4 S3 S2 S1 S0
D7 D6 D5 D4 D3 D2 D1 D0
S7 S6 S5 S4 S3 S2 S1 S0
D7 D6 D5 D4 D3 D2 D1 D0
1
2
34567
8
9
1
2
34567
8
9
1
2
34567
8
9
1
2
34567
8
9
SCL
ADDRESS
SUB ADDRESS
DATA
SUB ADDRESS
DATA
3589 F19
ACK
0
11
0
1
START
SDA
STOP
Figure 18. LTC3589/LTC3589-1 I2C Timing
tSU, DAT
tHD, STA
tHD, DAT
SDA
SCL
tHD, STA
tSU, STO
3589 F18
tBUF
tLOW
tHIGH
START
CONDITION
REPEATED START
CONDITION
STOP
START
tr
tf
tSP
OPERATION
I2C Bus Speed
The I2C port operates at speeds up to 400kHz. It has
built-in timing delays to ensure correct operation when
addressed from an I2C compliant master device. It also
contains input filters designed to suppress glitches should
the bus become corrupted.
I2C START and STOP Conditions
A bus master signals the beginning of communications
by transmitting a START condition. A START condition is
generated by transitioning SDA from HIGH to LOW while
SCL is HIGH. The master may transmit either the slave
write or the slave read address. Once data is written to
the LTC3589/LTC3589-1, the master may transmit a STOP
condition that commands the LTC3589/LTC3589-1 to act
upon its new command set. A STOP condition is sent by
the master by transitioning SDA from LOW to HIGH while
SCL is HIGH. The bus it then free for communication with
another I2C device.
I2C Byte Format
Each byte sent to or received from the LTC3589/LTC3589-1
must be 8 bits long followed by an extra clock cycle for the
acknowledge bit. The data should be sent to the LTC3589/
LTC3589-1 most significant bit (MSB) first.
I2C Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. When the LTC3589/LTC3589-1
is written to, it acknowledges its write address and sub-
sequent register address and data bytes. When reading
from the LTC3589/LTC3589-1, it acknowledges its read
address and 8-bit status byte.
An acknowledge pulse (active LOW) generated by the
LTC3589/LTC3589-1 lets the master know that the latest
byte of information was transferred. The master generates
the clock cycle and releases the SDA line (HIGH) during
the acknowledge clock cycle. The LTC3589/LTC3589-1
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