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參數(shù)資料
| 型號： | LTC3589IUJ-1#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING REGULATOR, 2600 kHz SWITCHING FREQ-MAX, PQCC40 |
| 封裝： | 6 X 6 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, QFN-40 |
| 文件頁數(shù)： | 10/46頁 |
| 文件大?。?/td> | 570K |
| 代理商： | LTC3589IUJ-1#TRPBF |
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LTC3589/LTC3589-1
18
3589fc
250mA LDO REGULATORS
Three LDO regulators on the LTC3589/LTC3589-1 will
each deliver up to 250mA output. The LDO regulators
are enabled by pin input or I2C command register. Pin
EN_LDO2 enables LDO2 and the LTC3589 EN_LDO34 pin
enables LDO3 and LDO4 together. An I2C command regis-
ter bit is available to decouple LDO4 from pin EN_LDO34
so that LDO4 is under command register control only.
The LTC3589-1 EN_LDO3 pin enables LDO3 only. LDO4
is controlled using the I2C command registers. All the
regulators have current limit protection circuits. When
disabled, a 2.5k internal pull-down resistor is connected
to the regulators output.
To help reduce LDO power loss in the system, the regula-
tors have dedicated supply inputs that may be lower than
the main VIN supply. Connect a low ESR 1μF capacitor to
each of the output pins LDO2, LDO3, and LDO4.
LDO Regulator 2
One of the LTC3589/LTC3589-1 dynamic slewing DACs
serves as the reference input of LDO2. The output range
of LDO2 is set using an external resistor divider connected
from LDO2 to the feedback pin LDO2_FB, as shown in
Figure 2. Set the output voltage of LDO2 using the fol-
lowing formula:
VOUT = 1+
R1
R2
(0.3625+L2DTVx 0.0125)
L2DTVx is the ve bit word contained in the LDO2 dynamic
target voltage 1 (L2DTV1) or the LDO2 dynamic target
voltage 2 (L2DTV2) command registers. The default value
of L2DTVx[4-0] is 11001 to output a reference voltage
of 0.675V. LDO2 is enabled by writing bit 4 in the output
voltage enable (OVEN) command register to 1 or driving
the LDO2_EN pin high. Whenever the command is given to
slew LDO2 DAC reference to a lower voltage an integrated
2.5k pull-down resistor is connected to LDO2 output.
Table 2. Shows the I2C command register settings used
to control LDO2.
Table 2. LDO 2 Command Register Settings
COMMAND
REGISTER[BIT]
VALUE
SETTING
OVEN[4]
0*
1
Disable
Enable
SCR2[4]
0*
1
Wait for Output Below 300mV Before Enable
Enable Immediately
VCCR[5]
0*
1
Select Register L2DTV1 (V1) Reference
Select Register L2DTV2 (V2) Reference
VCCR[6]
1
Initiate Dynamic Voltage Slew
VRRCR[7-6]
00
01
10
11*
Reference Slew Rate = 0.88mV/μs
Reference Slew Rate = 1.75mV/μs
Reference Slew Rate = 3.5mV/μs
Reference Slew Rate = 7mV/μs
L2DTV1[4-0]
11001*
DAC Dynamic Target Voltage V1
L2DTV1[5]
0*
1
Force PGOOD Low When Slewing
Normal PGOOD Operation When Slewing
L2DTV1[7]
0*
1
Shutdown LDO2 Normally
Keep LDO2 Alive
L2DTV2[4-0]
11001*
DAC Dynamic Target Voltage V2
* Denotes Default Power-On Value
OPERATION
3589 F02
PVIN
0.3625V
TO 0.75V
EA
FB
LDO2
R1
1μF
R2
DAC
5
Figure 2. LDO2 Application Circuit
–
+
3589 F01
VIN
0.8V
LDO1_FB
LDO1_STBY
R1
1μF
R2
Figure 1. Always-On LDO Application Circuit
LDO1_STBY is protected from short-circuits and over-
loading.
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