參數(shù)資料
型號: LTC3589EUJ#TRPBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: SWITCHING REGULATOR, 2600 kHz SWITCHING FREQ-MAX, PQCC40
封裝: 6 X 6 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, QFN-40
文件頁數(shù): 8/46頁
文件大小: 570K
代理商: LTC3589EUJ#TRPBF
LTC3589/LTC3589-1
16
3589fc
OPERATION
INTRODUCTION
The LTC3589/LTC3589-1 is a complete power manage-
ment solution for portable microprocessors and periph-
eral devices. It generates a total of eight voltage rails for
supplying power to the processor core, SDRAM, system
memory, PC cards, always-on real-time clock and HDD
functions. Supplying the voltage rails are an always-on
low quiescent current 25mA LDO, one 1.6A and two 1A
(1.2A for LTC3589-1) step-down regulators, a 1.2A buck-
boost regulator, and three 250mA low dropout regulators.
Supporting the multiple regulators is a highly congurable
power-on sequencing capability, dynamic voltage slewing
DAC output voltage control, a pushbutton interface con-
troller, regulator control via an I2C interface, and extensive
status and interrupt outputs.
The LTC3589/LTC3589-1 operates over an input supply
range of 2.7V to 5.5V. The input supplies for the 250mA
LDO regulators may operate as low as 1.7V to limit power
loss at low output voltages.
The always-on LDO1 provides a resistor programmable
output voltage as low as 0.8V and is capable of supplying
25mA. With only the always-on LDO active the LTC3589/
LTC3589-1 draws just 8μA (typical). Always-on LDO1 will
continue to operate with VIN levels as low as 2.0V (typical)
to maintain memory and RTC function as long as possible.
Each of the 250mA LDO regulators has unique output
voltage congurations. LDO3 has a xed 1.8V (2.8V for
LTC3589-1) output. LDO4 has four output levels selectable
via the I2C interface. Its possible outputs are 1.8V, 2.5V,
2.8V, and 3.3V. (1.2V, 1.8V, 2.5V, 3.2V for LTC3589-1) LDO2
has a dynamically slewing DAC set point reference and
an external feedback pin to set the output voltage range
with a resistive divider. Each LDO draws 60μA (typical)
quiescent current.
The LTC3589 includes three internally compensated con-
stant frequency current mode step-down switching regu-
lators two capable of supplying 1A of output current and
one capable of supplying 1.6A. The LTC3589-1 step-down
regulators can supply 1.2A, 1.2A, and 1.6A. Step-down
regulator switching frequencies of 2.25MHz or 1.125MHz
are independently selected for each step-down regulator
using the I2C command registers. The power-on default
frequency is 2.25MHz. Each of the step-down regulators
have dynamically slewing DAC input references and external
feedback pins to set output voltage range. The step-down
regulators three operating modes, pulse-skipping, burst,
or forced continuous, are set using the I2C interface. In
pulse-skipping mode the regulator will support 100%
duty cycle. For best efciency at low output loads select
Burst Mode operation. Forced continuous mode minimizes
output voltage ripple at light loads.
The 4-switch buck-boost DC/DC voltage mode converter
generates a user-programmable output voltage rail from
1.8V to 5V. Utilizing a proprietary switching algorithm,
the buck-boost converter maintains high efciency and
low noise operation with input voltages that are above,
below or equal to the required output rail. The buck-boost
error amplier uses a xed 0.8V reference and the output
voltage is set by an external resistor divider. Burst Mode
operation is enabled through the I2C control registers. No
external compensation components are required for the
buck-boost converter.
The reference inputs for the three step-down regulators
and LDO2 are 5-bit D to A converters with up-down ramp-
ing at selectable slew rates. The slew endpoint voltages
and select bits are stored in I2C registers for each DAC.
A select bit in the I2C command registers chooses which
register to use for each target voltage. Variable reference
slew rates from 0.88mV/μs to 7mV/μs are selectable in
the I2C register. Each of the four DACs has independent
voltage, voltage select, and slew rate control registers.
The LTC3589/LTC3589-1 is equipped with a pushbutton
control circuit that will activate the WAKE output, indicate
pushbutton status via the PBSTAT pin, and initiate a hard
reset shutdown of the regulators. Grounding the ON pin
with the pushbutton for 400ms will force the WAKE pin
to release HIGH. The WAKE pin output can be tied to the
enable pin of the rst regulator in a power-on sequence.
Once in the power-on state, subsequent pushes of the but-
ton longer than 50ms are mirrored by the PBSTAT output.
Holding ON LOW for ve seconds disables all the regula-
tors, pulls down the WAKE pin, and pulls down RSTO for
one second to indicate to the processor that a hard reset
occurred. All regulator enables and pushbutton inputs are
inhibited for one second following the hard reset.
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