參數(shù)資料
型號(hào)： LTC3589EUJ#TRPBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： SWITCHING REGULATOR, 2600 kHz SWITCHING FREQ-MAX, PQCC40
封裝： 6 X 6 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, QFN-40
文件頁(yè)數(shù)： 26/46頁(yè)
文件大?。?/td> 570K
代理商： LTC3589EUJ#TRPBF
LTC3589/LTC3589-1
32
3589fc
OPERATION
PGOOD Pin and PGSTAT Status Register Function
Each LTC3589/LTC3589-1 regulator has an internal power
good output that is active whenever the regulators feedback
pin is closer than 7% (typical) from its input reference
voltage. If any of the internal power good signals indicate
a low voltage for longer than 25μs (typical), the PGOOD
pin is pulled LOW and the appropriate bit in the PGSTAT
status register (Table 15) is set.
Table 15. PGSTAT Read-Only Register Bit Definitions
PGSTAT[BIT] VALUE
SETTING
00
1
LDO1_STBY Output Low
LDO1_STBY Output Good
10
1
Step-Down Switching Regulator 1 Output Low
Step-Down Switching Regulator 1 Output Good
20
1
Step-Down Switching Regulator 2 Output Low
Step-Down Switching Regulator 2 Output Good
30
1
Step-Down Switching Regulator 3 Output Low
Step-Down Switching Regulator 3 Output Good
40
1
Buck-Boost Regulator 4 Output Low
Buck-Boost Regulator 4 Output Good
50
1
LDO2 Output Low
LDO2 Output Good
60
1
LDO3 Output Low
LDO3 Output Good
70
1
LDO4 Output Low
LDO4 Output Good
Figure 14. PGOOD Pin and PGSTAT Status Register Timing
VOUTx
PGOOD
IRQ
3589 F14
ENx
200μs
25μs
1sec
14ms
250μs
ENABLE
DISABLE
UNDERVOLTAGE
DISABLED IF
WAKE LOW
WAKE HIGH AFTER 1sec
IF PWR_ON HIGH
EXTENDED
UNDERVOLTAGE
(FAULT)
WAKE
250μs
Figure 15. UV Detection Hard Reset and Warning Levels
VIN
UNDERVOLTAGE
VIN
FAULT
WARNING
3589 F15
2.55V
2.65V
2.9V
3V
the PGSTAT bits are HIGH 250μs after the last enabled
regulator is within 7% of its target.
If any enabled regulator output falls more than 7% low
for longer than 25μs PGOOD is pulled LOW and a cor-
responding status bit in the PGSTAT register is set to 0.
The PGOOD pin and PGSTAT status bit remain LOW for
as long as the low voltage condition persists plus 250μs.
An extended low output rail causing the PGOOD pin to
be LOW for longer than 14ms defines a PGOOD timeout
fault condition that triggers a hard reset if not masked in
I2C register bit SCR2[7]. When SCR2[7] is HIGH, PGOOD
remains in normal operation.
During a dynamic voltage slew, PGOOD is pulled LOW
unless bit 5 in the dynamic target voltage register for
each regulator is set HIGH. The status register PGSTAT
is unaffected by a dynamic voltage slew.
Undervoltage Detection
The LTC3589 undervoltage (UV) detection circuit will out-
put a fault condition, locking out regulator operation, until
VIN reaches 2.7V. Once VIN is above 2.7V the LTC3589/
LTC3589-1 will operate normally until VIN drops to 2.55V
(typical). When VIN drops below 2.55V, the fault condition
initiates a hard shutdown reset. Figure 15 shows under-
voltage warning and fault detection levels.
Figure 14 shows the PGOOD pin and PGSTAT status reg-
ister timing. When no regulator is enabled, the PGOOD
pin is pulled LOW and PGSTAT bits are LOW. PGOOD and
An undervoltage warning sets register bit IRQSTAT[4] and
pulls the IRQ pin LOW.
To minimize standby quiescent current the UVLO and
thermal sensor circuits are disabled when all the regula-
tors are off.
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