參數(shù)資料
型號(hào): LTC3409
廠商: Linear Technology Corporation
元件分類(lèi): DRAM
英文描述: 64 x 18 3.3-V asynchronous FIFO memory 56-SSOP 0 to 70
中文描述: 600mA的低輸入電壓降壓穩(wěn)壓器x 3mm DFN封裝采用3mm
文件頁(yè)數(shù): 13/16頁(yè)
文件大小: 246K
代理商: LTC3409
13
LTC3409
3409f
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
DS(ON)
).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (
I
LOAD
ESR), where ESR is the effective series
resistance of C
OUT
.
I
LOAD
also begins to charge or
discharge C
OUT
, which generates a feedback error signal.
The regulator loop then acts to return V
OUT
to its steady
state value. During this recovery time V
OUT
can be moni-
tored for overshoot or ringing that would indicate a stabil-
ity problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1
μ
F) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 C
LOAD
).
Thus, a 10
μ
F capacitor charging to 3.3V would require a
250
μ
s rise time, limiting the charging current to about
130mA.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3409. These items are also illustrated graphically in
the layout diagram of Figure 3. Check the following in your
layout.
1. Does the capacitor C
IN
connect to the power V
IN
(Pins 3, 4) and GND (Exposed Pad) as close as pos-
sible This capacitor provides the AC current to the
internal power MOSFETs and their drivers.
2. Are the C
OUT
and L1 closely connected The (–) plate of
C
OUT
returns current to GND and the (–) plate of C
IN
.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C
OUT
and a ground sense line
terminated near GND (Exposed Pad). The feedback
signals V
FB
should be routed away from noisy compo-
nents and traces, such as the SW line (Pins 6), and its
trace should be minimized.
4. Keep sensitive components away from the SW pins.
The input capacitor C
IN
and the resistors R1 and R2
should be routed away from the SW traces and the
inductors.
5. A ground plane is preferred, but if not available, keep the
signal and power grounds segregated with small signal
components returning to the GND pin at one point. They
should not share the high current path of C
IN
or C
OUT
.
6. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power components. These copper areas should be
connected to V
IN
or GND.
APPLICATIU
W
U
U
V
IN
LTC3409
RUN
V
FB
V
IN
SYNC
MODE
SW
L1
C1
C
IN
R1
R2
V
IN
SGND GND
C
OUT
3409 F03
V
OUT
Figure 3
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