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參數(shù)資料
| 型號： | LTC3104IMSE#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 339K |
| 描述： | IC REG DL BCK/LINEAR SYNC 16MSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 拓?fù)洌?/td> | 降壓（降壓）同步（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 2 |
| 頻率 - 開關(guān)： | 1.2MHz |
| 電壓/電流 - 輸出 1： | 0.6 V ~ 13.8 V，300mA |
| 電壓/電流 - 輸出 2： | 0.6 V ~ 14.5 V，10mA |
| 帶 LED 驅(qū)動器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 無 |
| 電源電壓： | 2.5 V ~ 15 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TFSOP（0.118"，3.00mm 寬）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-MSOP，裸露焊盤 |
| 包裝： | 帶卷 (TR) |
LTC3104
15
3104f
APPLICATIONS INFORMATION
V
IN
voltage requirements. If used, note that the external
divider current is not included in the LTC3104 quiescent
current specification.
The rising UVLO threshold can be calculated using the
following equation:
V
UVLO
=0.8V 1+
R6
R5
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
For most applications a 0.022礔 will suffice. The capaci-
tor should be placed as close to the respective pins as
possible.
LDO Output Capacitor Selection
The LDO is designed to be stable with a minimum 4.7礔
output capacitor. No series resistor is required when using
low ESR capacitors. For most applications, a 10礔 ceramic
capacitor is recommended. Larger values will improve
transient response and raise the power supply rejection
ratio (PSRR) of the LDO.
LDO Output Voltage Programming
The output voltage is set by a resistive divider according
to the following formula:
V
LDO
=0.6V 1+
R4
R3
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
The external divider is connected to the LDO output, V
LDO
,
as shown in Figure 3. Similar to the buck feedback network,
a feedforward capacitor may be placed in parallel with
resistor R4 for improved transient response. For resistor
values of ~1M a 12pF ceramic capacitor will suffice.
Figure 2. Setting the Undervoltage Lockout Threshold
RUN
LTC3104
GND
IN
R5
R6
3104 F02
FBLDO
R4
R3
C
FF2
3104 F03
V
LDO
GND
LTC3104
Figure 3. Setting the LDO Output Voltage
14
13
10
11
12
4
5
3
2
1
V
INLDO
V
LDO
FBLDO
FB
RUN
V
CC
NC
MODE
V
IN
SW
BST
GND
RUNLDO
PGOOD
6
7
9
8
KELVIN TO V
OUT
V
INLDO
V
LDO
3104 F04
UNINTERRUPTED GROUND PLANE
SHOULD EXIST UNDER ALL COMPONENTS
SHOWN AND UNDER THE TRACES
CONNECTING THOSE COMPONENTS
V
OUT
VIA GROUND PLANE
V
IN
Figure 4. PCB Layout Recommendations
Internal V
CC
Regulator
The LTC3104 uses an internal NMOS source follower
regulator off of V
IN
to generate a low voltage internal rail,
V
CC
. The regulator is designed to deliver current only to
the internal drivers and other internal control circuits and
not to an external load. The V
CC
pin should be bypassed
with a 1礔 or larger ceramic capacitor.
Boost Capacitor Selection
The LTC3104 uses a bootstrapped supply to power the
buck switch gate drivers. When the synchronous rectifier
turns on, an internal PMOS switch turns on synchronously
to charge the boost capacitor, C
BST
, to the voltage on V
CC
.
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