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參數(shù)資料
| 型號(hào)： | LTC2900 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Octal Buffer/Driver With 3-State OUtputs 20-TVSOP -40 to 85 |
| 中文描述： | 可編程四路電源監(jiān)視器可調(diào)復(fù)位定時(shí)器 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 199K |
| 代理商： | LTC2900 |
7
LTC2900
2900f
V3 (Pin 1):
Voltage Input 3. Select from 2.5V, 1.8V, 1.5V
or ADJ. See Table 1 for details.
V1 (Pin 2):
Voltage Input 1. Select from 5V or 3.3V. See
Table 1 for details. The greater of (V1, V2) is also V
CC
for
the device. Bypass this pin to ground with a 0.1
μ
F (or
greater) capacitor.
CRT (Pin 3):
Reset Delay Time Programming Pin. Attach
an external capacitor (C
RT
) to GND to set a reset delay time
of 4.6ms/nF. Leaving the pin open generates a minimum
delay of approximately 50
μ
s. A 47nF capacitor will gener-
ate a 216ms reset delay time.
RST (Pin 4):
Reset Logic Output. Active low with weak
pull-up to V2 (LTC2900-1) or active pull-up to V2
(LTC2900-2). Pulls low when any voltage input is below
the reset threshold and held low for the programmed delay
time after all voltage inputs are above threshold. May be
pulled above V2 using an external pull-up (LTC2900-1
only).
PBR (Pin 5):
Manual Reset Pin. Attach a push-button
switch between this pin and ground. A logic low on this pin
will pull RST low. When the PBR pin returns high, RST will
return high after the programmed reset delay assuming all
four voltage inputs are above threshold. A weak internal
pull-up allows the pin to be left floating for normal monitor
operation. When using a switch, the switch is debounced
through the reset circuitry using the delay provided by the
C
RT
timing capacitor.
GND (Pin 6):
Ground.
V
PG
(Pin 7):
Voltage Threshold Combination Select Input.
Connect to an external 1% resistive divider between V
REF
and GND to select 1 of 16 combinations of preset and/or
±
adjustable voltage thresholds (see Table 1). Do not add
capacitance on the V
PG
pin.
V
REF
(Pin 8):
Buffered Reference Voltage. A 1.210V
nominal reference used for the programming voltage
(V
PG
) and for the offset of negative adjustable applica-
tions. The buffered reference can source and sink up to
1mA. The reference can drive a bypass capacitor of up to
1000pF without oscillation.
V4 (Pin 9):
Voltage Input 4. Select from 1.8V, 1.5V, ADJ or
–ADJ. See Table 1 for details.
V2 (Pin 10):
Voltage Input 2. Select from 3.3V, 3V or 2.5V.
See Table 1 for details. The greater of (V1, V2) is also V
CC
for the device. Bypass this pin to ground with a 0.1
μ
F (or
greater) capacitor. RST is weakly pulled up to V2
(LTC2900-1). RST is actively pulled up to V2 in the
LTC2900-2.
PIU
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