參數(shù)資料
型號(hào)： LTC2621
廠商： Linear Technology Corporation
英文描述： 18-Bit Universal Bus Driver With 3-State Outputs 56-TSSOP -40 to 85
中文描述： 16/14/12軌到軌DAC的10引腳DFN
文件頁(yè)數(shù)： 9/16頁(yè)
文件大?。?/td> 321K
代理商： LTC2621
9
LTC2601/LTC2611/LTC2621
2601f
PI
FU
CTIO
N
S
U
U
SDO (Pin 1):
Serial Interface Data Output. The serial
output of the shift register appears at the SDO pin. The data
transferred to the device via the SDI pin is delayed 32 SCK
rising edges before being output at the next falling edge.
This pin is used for daisy-chain operation.
SDI (Pin 2):
Serial Interface Data Input. Data is applied to
SDI for transfer to the device at the rising edge of SCK
(Pin3). The LTC2601 accepts input word lengths of either
24 or 32 bits.
SCK (Pin 3):
Serial Interface Clock Input. CMOS and TTL
compatible.
CLR (Pin 4):
Asynchronous Clear Input. A logic low at this
level-triggered input clears all registers and causes the
DAC voltage outputs to drop to 0V. CMOS and TTL
compatible.
CS/LD (Pin 5):
Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on SDI
into the register. When CS/LD is taken high, SCK is
disabled and the specified command (see Table 1) is
executed.
REF (Pin 6):
Reference Voltage Input. 0V
≤
V
REF
≤
V
CC
.
V
OUT
(Pin 7):
DAC Analog Voltage Output. The output
range is 0V to V
REF
.
GND (Pin 8):
Analog Ground.
V
CC
(Pin 9):
Supply Voltage Input. 2.5V
≤
V
CC
≤
5.5V.
LDAC (Pin 10):
Asynchronous DAC Update Pin. If CS/LD
is high, a falling edge on LDAC immediately updates the
DAC register with the contents of the input register (simi-
lar to a software update). If CS/LD is low when LDAC goes
low, the DAC register is updated after CS/LD returns high.
A low on the LDAC pin powers up the DAC. A software
power down command is ignored if LDAC is low.
Exposed Pad (Pin 11):
Ground. Must be soldered to PCB
ground.
相關(guān)PDF資料
PDF描述
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LTC2846IG 3.3V Software-Selectable Multiprotocol Transceiver with Termination
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