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參數(shù)資料
| 型號： | LTC2621 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 18-Bit Universal Bus Driver With 3-State Outputs 56-TSSOP -40 to 85 |
| 中文描述： | 16/14/12軌到軌DAC的10引腳DFN |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 321K |
| 代理商： | LTC2621 |
15
LTC2601/LTC2611/LTC2621
2601f
Figure 3. Effects of Rail-to-Rail Operation On the DAC Transfer Curve. (a) Overall Transfer Function (b) Effect
of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
OPERATIOU
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
2601 F03
INPUT CODE
(b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
32, 768
INPUT CODE
(a)
0
65, 535
OUTPUT
VOLTAGE
V
REF
= V
CC
V
REF
= V
CC
(c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
U
PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm
×
3mm)
(Reference LTC DWG # 05-08-1699)
3.00
±
0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.38
±
0.10
BOTTOM VIEW—EXPOSED PAD
1.65
±
0.10
(2 SIDES)
0.75
±
0.05
R = 0.115
TYP
2.38
±
0.10
(2 SIDES)
1
5
10
6
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD10) DFN 1103
0.25
±
0.05
2.38
±
0.05
(2 SIDES)
RECOMMENDED
SOLDER PAD PITCH AND DIMENSIONS
1.65
±
0.05
(2 SIDES)
2.15
±
0.05
0.50
BSC
0.675
±
0.05
3.50
±
0.05
PACKAGE
OUTLINE
0.25
±
0.05
0.50 BSC
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