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參數(shù)資料
| 型號(hào)： | LTC2607CDE |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | DAC |
| 英文描述： | 16-/14-/12-Bit Dual Rail-to-Rail DACs with I2C Interface |
| 中文描述： | SERIAL INPUT LOADING, 10 us SETTLING TIME, 16-BIT DAC, PDSO12 |
| 封裝： | 4 X 3 MM, EXPOSED PAD, PLASTIC, MO-229WGED, DFN-12 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 318K |
| 代理商： | LTC2607CDE |
13
LTC2607/LTC2617/LTC2627
26071727f
The value of these pull-up resistors is dependent on the
power supply and can be obtained from the I
2
C specifica-
tions. For an I
2
C bus operating in the fast mode, an active
pull-up will be necessary if the bus capacitance is greater
than 200pF.
The LTC2607/LTC2617/LTC2627 are receive-only (slave)
devices. The master can write to the LTC2607/LTC2617/
LTC2627. The LTC2607/LTC2617/LTC2627 do not re-
spond to a read from the master.
The START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communica-
tion to a slave device by transmitting a START condition.
A START condition is generated by transitioning SDA from
high to low while SCL is high.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while SCL
is high. The bus is then free for communication with
another I
2
C device.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The Acknowledge re-
lated clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave-receiver must pull down the SDA
bus line during the Acknowledge clock pulse so that it
remains a stable LOW during the HIGH period of this clock
pulse. The LTC2607/LTC2617/LTC2627 respond to a
write by a master in this manner. The LTC2607/LTC2617/
LTC2627 do not acknowledge a read (retains SDA HIGH
during the period of the Acknowledge clock pulse).
Chip Address
The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set to
any one of three states: V
CC
, GND or float. This results in
OPERATIOU
Power-On Reset
The LTC2607/LTC2617/LTC2627 clear the outputs to
zero scale when power is first applied, making system
initialization consistent and repeatable. The LTC2607-1/
LTC2617-1/LTC2627-1 set the voltage outputs to midscale
when power is first applied.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2607/
LTC2617/LTC2627 contain circuitry to reduce the power-
on glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground (typ) during power-on. See Power-On Reset Glitch
in the Typical Performance Characteristics section.
Power Supply Sequencing
The voltage at REF (Pin 9) should be kept within the range
–0.3V
≤
V
REF
≤
V
CC
+ 0.3V (see Absolute Maximum
Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at V
CC
(Pin
8
) is in transition.
Transfer Function
The digital-to-analog transfer function is:
V
k
N
2
V
V
V
OUT IDEAL
(
REF
REFLO
REFLO
)
=
(
)
+
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and V
REF
is the voltage at
REF (Pin 6).
Serial Digital Interface
The LTC2607/LTC2617/LTC2627 communicate with a host
using the standard 2-wire I
2
C interface. The Timing Dia-
grams (Figures 1 and 2) show the timing relationship of
the signals on the bus. The two bus lines, SDA and SCL,
must be high when the bus is not in use. External pull-up
resistors or current sources are required on these lines.
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