參數(shù)資料
型號: LTC2601
廠商: Linear Technology Corporation
英文描述: 16-/14-/12-Bit Rail-to-Rail DACs in 10-Lead DFN
中文描述: 16/14/12軌到軌DAC的10引腳DFN
文件頁數(shù): 4/16頁
文件大?。?/td> 321K
代理商: LTC2601
4
LTC2601/LTC2611/LTC2621
2601f
TIW
range, otherwise specifications are at T
A
= 25
°
C. (See Figure 1) (Note 4)
The
G
denotes specifications which apply over the full operating temperature
Note 1:
Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2:
Linearity and monotonicity are defined from code k
L
to code
2
N
– 1, where N is the resolution and k
L
is given by k
L
= 0.016(2
N
/V
REF
),
rounded to the nearest whole code. For V
REF
= 4.096V and N = 16, k
L
=
256 and linearity is defined from code 256 to code 65,535.
Note 3:
Digital inputs at 0V or V
CC
.
Note 4:
Guaranteed by design and not production tested.
Note 5:
Inferred from measurement at code K
L
= 0.016(2
N
/V
REF
) and at
full scale.
Note 6:
V
CC
= 5V, V
REF
= 4.096V. DAC is stepped 1/4 scale to 3/4 scale
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 7:
V
CC
= 5V, V
REF
= 4.096V. DAC is stepped
±
1LSB between half
scale and half scale – 1. Load is 2k in parallel with 200pF to GND.
ELECTRICAL C
temperature range, otherwise specifications are at T
A
= 25
°
C. REF = 4.096V (V
CC
= 5V), REF = 2.048V (V
CC
= 2.5V), V
OUT
unloaded,
unless otherwise noted.
HARA TERISTICS
The
G
denotes specifications which apply over the full operating
LTC2621
TYP
LTC2611
TYP
LTC2601
TYP
SYMBOL
AC Performance
t
S
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
Settling Time (Note 6)
±
0.024% (
±
1LSB at 12 Bits)
±
0.006% (
±
1LSB at 14 Bits)
±
0.0015% (
±
1LSB at 16 Bits)
±
0.024% (
±
1LSB at 12 Bits)
±
0.006% (
±
1LSB at 14 Bits)
±
0.0015% (
±
1LSB at 16 Bits)
7
7
9
7
9
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
10
2.7
4.8
5.2
0.80
1000
12
180
120
100
15
Settling Time for 1LSB Step
(Note 7)
2.7
2.7
4.8
Voltage Output Slew Rate
Capacitive Load Driving
Glitch Impulse
Multiplying Bandwidth
Output Voltage Noise Density
0.80
1000
12
180
120
100
15
0.80
1000
12
180
120
100
15
V/
μ
s
pF
nV s
kHz
nV/
Hz
nV/
Hz
μ
V
P-P
At Midscale Transition
e
n
At f = 1kHz
At f = 10kHz
0.1Hz to 10Hz
Output Voltage Noise
LTC2601/LTC2611/LTC2621
MIN
SYMBOL
V
CC
= 2.5V to 5.5V
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
PARAMETER
CONDITIONS
TYP
MAX
UNITS
SDI Valid to SCK Setup
SDI Valid to SCK Hold
SCK High Time
SCK Low Time
CS/LD Pulse Width
LSB SCK High to CS/LD High
CS/LD Low to SCK High
SDO Propagation Delay from SCK Falling Edge
G
4
4
9
9
ns
ns
ns
ns
ns
ns
ns
G
G
G
G
10
7
7
G
G
C
LOAD
= 10pF
V
CC
= 4.5V to 5.5V
V
CC
= 2.5V to 5.5V
G
G
20
45
ns
ns
ns
ns
ns
ns
t
9
t
10
t
12
t
13
CLR Pulse Width
CS/LD High to SCK Positive Edge
LDAC Pulse Width
CS/LD High to LDAC High or Low Transition
SCK Frequency
G
20
7
15
200
G
G
G
50% Duty Cycle
G
50
MHz
相關PDF資料
PDF描述
LTC2601CDD 16-/14-/12-Bit Rail-to-Rail DACs in 10-Lead DFN
LTC2601IDD 18-Bit Universal Bus Driver With 3-State Outputs 56-TSSOP -40 to 85
LTC2611CDD 16-/14-/12-Bit Rail-to-Rail DACs in 10-Lead DFN
LTC2621 18-Bit Universal Bus Driver With 3-State Outputs 56-TSSOP -40 to 85
LTC2846 Replaced by SN74ALVCH16901 : 18-Bit Universal Bus Transceiver with Parity Generators/Checkers 64-TSSOP -40 to 85
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