參數(shù)資料
型號(hào)： LTC2495IUHF#TR
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 16-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC38
封裝： 5 X 7 MM, PLASTIC, MO-220WKHD, QFN-38
文件頁(yè)數(shù)： 28/32頁(yè)
文件大小： 619K
代理商： LTC2495IUHF#TR
LTC2495
2495fa
power requiremenTs The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC
Supply Voltage
●
2.7
5.5
V
ICC
Supply Current
Conversion Current (Note 11)
Temperature Measurement (Note 11)
Sleep Mode (Note 11)
●
160
200
1
275
300
2
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fEOSC
External Oscillator Frequency Range
(Note 16)
●
10
4000
kHz
tHEO
External Oscillator High Period
●
0.125
100
s
tLEO
External Oscillator Low Period
●
0.125
100
s
tCONV_1
Conversion Time for 1x Speed Mode
50Hz Mode
60Hz Mode
Simultaneous 50Hz/60Hz Mode
External Oscillator (Note 10)
●
157.2
131
144.1
160.3
133.6
146.9
41036/fEOSC (in kHz)
163.5
136.3
149.9
ms
tCONV_2
Conversion Time for 2x Speed Mode
50Hz Mode
60Hz Mode
Simultaneous 50Hz/60Hz Mode
External Oscillator (Note 10)
●
78.7
65.6
72.2
80.3
66.9
73.6
20556/fEOSC (in kHz)
81.9
68.2
75.1
ms
DigiTal inpuTs anD DigiTal ouTpuTs The
●
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSCL
SCL Clock Frequency
●
0
400
kHz
tHD(SDA)
Hold Time (Repeated) Start Condition
●
0.6
s
tLOW
Low Period of the SCL Pin
●
1.3
s
tHIGH
High Period of the SCL Pin
●
0.6
s
tSU(STA)
Set-Up Time for a Repeated Start Condition
●
0.6
s
tHD(DAT)
Data Hold Time
●
0
0.9
s
tSU(DAT)
Data Set-Up Time
●
100
ns
tr
Rise Time for SDA Signals
(Note 14)
●
20 + 0.1CB
300
ns
tf
Fall Time for SDA Signals
(Note 14)
●
20 + 0.1CB
300
ns
tSU(STO)
Set-Up Time for Stop Condition
●
0.6
s
tBUF
Bus Free Time Between a Second Start Condition
●
1.3
s
i2c Timing characTerisTics The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3, 15)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: Unless otherwise specified: VCC = 2.7V to 5.5V
VREFCM = VREF/2, FS = 0.5VREF/Gain
VIN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2,
where IN+ and IN– are the selected input channels.
Note 4: Use internal conversion clock or external conversion clock source
with fEOSC = 307.2kHz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external oscillator).
Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external oscillator).
Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC =
280kHz ±2% (external oscillator).
Note 10: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 11: The converter uses its internal oscillator.
Note 12: The output noise includes the contribution of the internal
calibration operations.
Note 13: Guaranteed by design and test correlation.
Note 14: CB = capacitance of one bus line in pF (10pF ≤ CB ≤ 400pF).
Note 15: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 16: Refer to Applications Information section for Performance vs
Data Rate graphs.
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