參數(shù)資料
型號： LTC2494CUHF#PBF
廠商： Linear Technology
文件頁數(shù)： 27/38頁
文件大小： 0K
描述： IC ADC 16BIT W/PGA 38-QFN
標(biāo)準(zhǔn)包裝： 52
位數(shù)： 16
采樣率（每秒）： 15
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 480µW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 38-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 38-QFN（5x7）
包裝： 管件
輸入數(shù)目和類型： 16 個單端，雙極；8 個差分，雙極
配用： DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494
LTC2494
2494fd
applications inForMation
The user can expect to achieve this level of performance
using the internal oscillator, as shown in Figures 23, 24
and 25. Measured values of normal mode rejection are
shown superimposed over the theoretical values in all
three rejection modes.
Traditional high order delta-sigma modulators suffer
from potential instabilities at large input signal levels.
The proprietary architecture used for the LTC2494 third
order modulator resolves this problem and guarantees
stability with input signals 150% of full-scale. In many
industrial applications, it is not uncommon to have mi-
crovolt level signals superimposed over unwanted volt
level error sources with several volts of peak-to-peak
noise. Figures 26 and 27 show measurement results for
the rejection of a 7.5V peak-to-peak noise source (150%
of full-scale) applied to the LTC2494. From these curves,
it is shown that the rejection performance is maintained
even in extremely noisy environments.
Using the 2x speed mode of the LTC2494 alters the rejec-
tion characteristics around DC and multiples of fS. The
device bypasses the offset calibration in order to increase
the output rate. The resulting rejection plots are shown
in Figures 28 and 29. 1x type frequency rejection can be
achieved using the 2x mode by performing a running
average of the conversion results (see Figure 30).
Output Data Rate
Whenusingitsinternaloscillator,theLTC2494producesup
to 15 samples per second (sps) with a notch frequency of
60Hz. The actual output data rate depends upon the length
of the sleep and data output cycles which are controlled
by the user and can be made insignificantly short. When
operating with an external conversion clock (fO connected
to an external oscillator), the LTC2494 output data rate
can be increased. The duration of the conversion cycle is
41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves
as if the internal oscillator is used.
AnincreaseinfEOSCoverthenominal307.2kHzwilltranslate
into a proportional increase in the maximum output data
rate (up to a maximum of 100sps). The increase in output
rate leads to degradation in offset, full-scale error, and ef-
fective resolution as well as a shift in frequency rejection.
Whenusingtheintegratedtemperaturesensor,theinternal
Figure 23. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (60Hz Notch)
Figure 24. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (50Hz Notch)
Figure 25. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (50Hz/60Hz Notch)
INPUT FREQUENCY (Hz)
0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240
NORMAL
MODE
REJECTION
(dB)
2494 F23
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
MEASURED DATA
CALCULATED DATA
INPUT FREQUENCY (Hz)
0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
NORMAL
MODE
REJECTION
(dB)
2494 F24
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
MEASURED DATA
CALCULATED DATA
INPUT FREQUENCY (Hz)
0
20
40
60
80
100
120
140
160
180
200
220
NORMAL
MODE
REJECTION
(dB)
2494 F25
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
MEASURED DATA
CALCULATED DATA
oscillator should be used (fO = 0) or an external oscillator
applied to fO, fEOSC, should be set to 307.2kHz Max.
A change in fEOSC results in a proportional change in the
internal notch position. This leads to reduced differential
mode rejection of line frequencies. The common mode
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