參數(shù)資料
型號(hào)： LTC2494CUHF#PBF
廠商： Linear Technology
文件頁數(shù)： 16/38頁
文件大?。?/td> 0K
描述： IC ADC 16BIT W/PGA 38-QFN
標(biāo)準(zhǔn)包裝： 52
位數(shù)： 16
采樣率（每秒）： 15
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 480µW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 38-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 38-QFN（5x7）
包裝： 管件
輸入數(shù)目和類型： 16 個(gè)單端，雙極；8 個(gè)差分，雙極
配用： DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494
LTC2494
2494fd
applications inForMation
edge). The channel selection and converter configuration
mode will be used for the following conversion cycle. If
the input channel or converter configuration is changed
during this I/O cycle, the new settings take effect on the
conversion cycle following the data input/output cycle.
The output data is shifted out the SDO pin on each falling
edge of SCK. This enables external circuitry to latch the
output on the rising edge of SCK. EOC can be latched on
the first rising edge of SCK and the last bit of the conver-
sion result can be latched on the 24th rising edge of SCK.
On the 24th falling edge of SCK, the device begins a new
conversion and SDO goes HIGH (EOC = 1) indicating a
conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Typically, CS remains LOW during the data output/input
state. However, the data output state may be aborted by
pulling CS HIGH any time between the 1st falling edge
and the 24th falling edge of SCK (see Figure 7). On the
rising edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of CS occurs after the 8th falling edge
of SCK, the new input channel is loaded and valid for the
next conversion cycle. If CS goes HIGH between the 8th
falling edge and the 16th falling edge of SCK, the new
channel is still loaded, but the converter configuration
remains unchanged. In order to program both the input
channel and converter configuration, CS must go HIGH
after the 16th falling edge of SCK (at this point all data
has been shifted into the device).
Figure 6. External Serial Clock, Single Cycle Operation
Hi-Z
2494 F06
Hi-Z
CS
SCK
(EXTERNAL)
SDI
SDO
CONVERSION
SLEEP
DATA INPUT/OUTPUT
CONVERSION
VCC
fO
REF+
REF–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28
35
29
30
8
15
16
23
7
38
37
1,3,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
10F
0.1F
LTC2494
2.7V TO 5.5V
4-WIRE
SPI INTERFACE
EOC
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11
BIT 21
BIT 22
BIT 23
BIT 10 BIT 9
BIT 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
1
0
EN
SGL
A2
A1
A0
EN2
IM
FA
FB
SPD
GS2
GS1
GS0
ODD
DON'T CARE
MSB
SIG
“0”
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