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參數(shù)資料
| 型號： | LTC2492IDE |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 4-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO14 |
| 封裝： | 4 X 3 MM, PLASTIC, MO-229WGED-3, QFN-14 |
| 文件頁數(shù)： | 9/36頁 |
| 文件大?。?/td> | 652K |
| 代理商： | LTC2492IDE |
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LTC2492
2492fa
applicaTions inFormaTion
Bit 28 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 29 also pro-
vides underrange and overrange indication. If both Bit 29
and Bit 28 are HIGH, the differential input voltage is above
+FS. If both Bit 29 and Bit 28 are LOW, the differential
input voltage is below –FS. The function of these bits is
summarized in Table 1.
Table 1. LTC2492 Status Bits
Input Range
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
VIN ≥ 0.5 VREF
0
1
0V ≤ VIN < 0.5 VREF
0
1
0
–0.5 VREF ≤ VIN < 0V
0
1
VIN < –0.5 VREF
0
Bits 28 to 5 are the 24-bit conversion result MSB first.
Bit 5 is the least significant bit (LSB24).
Bits 4 to 0 are sub LSBs below the 24-bit level. Bits 4 to
0 may be included in averaging or discarded without loss
of resolution.
Data is shifted out of the SDO pin under control of the
serial clock (SCk) (see Figure 3). Whenever CS is HIGH,
SDO remains high impedance and SCk is ignored.
In order to shift the conversion result out of the device,
CS must first be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes in real
time as a function of the internal oscillator or the clock
applied to the fO pin from HIGH to LOW at the completion
of a conversion. This signal may be used as an interrupt
for an external microcontroller. Bit 31 (EOC) can be cap-
tured on the first rising edge of SCk. Bit 30 is shifted out
of the device on the first falling edge of SCk. The final
data bit (Bit 0) is shifted out on the on the falling edge of
the 31st SCk and may be latched on the rising edge of
the 32nd SCk pulse. On the falling edge of the 32nd SCk
pulse, SDO goes HIGH indicating the initiation of a new
conversion cycle. This bit serves as EOC (Bit 31) for the
next conversion cycle. Table 2 summarizes the output
data format.
As long as the voltage on the IN+ and IN– pins remains
between –0.3V and VCC + 0.3V (absolute maximum op-
erating range) a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 VREF to
+FS = 0.5 VREF. For differential input voltages greater
than +FS, the conversion result is clamped to the value
corresponding to +FS + 1LSB. For differential input volt-
ages below –FS, the conversion result is clamped to the
value –FS – 1LSB.
INPUT DATA FORMAT
The LTC2492 serial input word is 13 bits long and contains
twodistinctsetsofdata.Thefirstset(SGL,ODD,A2,A1,A0)
is used to select the input channel. The second set of data
(IM, FA, FB, SPD) is used to select the frequency rejection,
speed mode (1x, 2x), and temperature measurement.
After power up, the device initiates an internal reset cycle
whichsetstheinputchanneltoCH0toCH1(IN+=CH0,IN–=
CH1),thefrequencyrejectiontosimultaneous50Hz/60Hz,
and 1x output rate (auto-calibration enabled). The first
EOC
CS
SCK
(EXTERNAL)
SDI
SDO
2492 F03
CONVERSION
SLEEP
DATA INPUT/OUTPUT
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19
SIG
BIT 29
“0”
BIT 30
BIT 31
1
0
EN
SGL
A2
A1
A0
EN2
IM
FA
FB
SPD
ODD
BIT 18 BIT 17
BIT 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
DON'T CARE
Figure 3. Channel Selection, Configuration Selection and Data Output Timing
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