參數(shù)資料
型號(hào)： LTC2492IDE
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 4-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO14
封裝： 4 X 3 MM, PLASTIC, MO-229WGED-3, QFN-14
文件頁(yè)數(shù)： 26/36頁(yè)
文件大?。?/td> 652K
代理商： LTC2492IDE
LTC2492
2492fa
applicaTions inFormaTion
Using the 2x speed mode of the LTC2492 alters the rejec-
tion characteristics around DC and multiples of fS. The
device bypasses the offset calibration in order to increase
the output rate. The resulting rejection plots are shown
in Figures 27 and 28. 1x type frequency rejection can be
achieved using the 2x mode by performing a running
average of the conversion results (see Figure 29).
Output Data Rate
Whenusingitsinternaloscillator,theLTC2492producesup
to 7.5 samples per second (sps) with a notch frequency of
60Hz. The actual output data rate depends upon the length
of the sleep and data output cycles which are controlled
by the user and can be made insignificantly short. When
operating with an external conversion clock (FOconnected
to an external oscillator), the LTC2492 output data rate
can be increased. The duration of the conversion cycle is
41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves
as if the internal oscillator is used.
AnincreaseinfEOSCoverthenominal307.2kHzwilltranslate
into a proportional increase in the maximum output data
rate (up to a maximum of 100sps). The increase in output
rate leads to degradation in offset, full-scale error, and ef-
fective resolution as well as a shift in frequency rejection.
Whenusingtheintegratedtemperaturesensor,theinternal
oscillator should be used or an external oscillator, fEOSC
= 307.2kHz maximum.
A change in fEOSC results in a proportional change in the
internal notch position. This leads to reduced differential
mode rejection of line frequencies. The common mode
rejectionoflinefrequenciesremainsunchanged,thusfully
differential input signals with a high degree of symmetry
on both the IN+ and IN– pins will continue to reject line
frequency noise.
An increase in fEOSC also increases the effective dynamic
input and reference current. External RC networks will
continue to have zero differential input current, but the
time required for complete settling (580ns for fEOSC =
307.2kHz) is reduced, proportionally.
Once the external oscillator frequency is increased above
1MHz(amorethan3xincreaseinoutputrate)theeffective-
ness of internal auto calibration circuits begins to degrade.
This results in larger offset errors, full scale errors, and
decreased resolution (see Figures 30 to 37).
INPUT SIGNAL FREQUENCY (fN)
INPUT
NORMAL
REJECTION
(dB)
2492 F27
0
–20
–40
–60
–80
–100
–120
0
fN 2fN 3fN 4fN 5fN 6fN 7fN 8fN
Figure 27. Input Normal Mode Rejection 2x Speed Mode
INPUT SIGNAL FREQUENCY (fN)
INPUT
NORMAL
REJECTION
(dB)
2492 F28
0
–20
–40
–60
–80
–100
–120
250
248
252 254 256 258 260 262 264
Figure 28. Input Normal Mode Rejection 2x Speed Mode
相關(guān)PDF資料
PDF描述
LTC2492IDE#TR 4-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO14
LTC2494CUHF 16-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC38
LTC2494IUHF#TR 16-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC38
LTC2494IUHF 16-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC38
LTC2494CUHF#TR 16-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC38
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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