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參數(shù)資料
| 型號(hào)： | LTC2492IDE#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 4-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO14 |
| 封裝： | 4 X 3 MM, PLASTIC, MO-229WGED-3, QFN-14 |
| 文件頁數(shù)： | 3/36頁 |
| 文件大?。?/td> | 652K |
| 代理商： | LTC2492IDE#TR |
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LTC2492
2492fa
pin FuncTions
FO(Pin1):FrequencyControlPin.Digitalinputthatcontrols
the internal conversion clock rate. When FO is connected
to GND, the converter uses its internal oscillator running at
307.2kHz.Theconversionclockmayalsobeoverriddenby
driving the FO pin with an external clock in order to change
the output rate and the digital filter rejection null.
SDI (Pin 2): Serial Data Input. This pin is used to select
the line frequency rejection mode, 1x or 2x speed mode,
temperaturesensor,aswellastheinputchannel.Theserial
data input is applied under control of the serial clock (SCk)
duringthedataoutput/inputoperation.Thefirstconversion
following a new input or mode change is valid.
SCK(Pin3):Bidirectional,DigitalI/O,ClockPin.InInternal
Serial Clock Operation mode, SCk is generated internally
and is seen as an output on the SCk pin. In External Serial
Clock Operation mode, the digital I/O clock is externally
applied to the SCk pin. The Serial Clock operation mode
is determined by the logic level applied to the SCk pin at
power up and during the most recent falling edge of CS.
CS (Pin 4): Active LOW Chip Select. A LOW on this pin
enables the digital input/output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the data output aborts the data transfer and starts
a new conversion.
SDO (Pin 5): Three-State Digital Output. During the data
output period, this pin is used as the serial data output.
When the chip select pin is HIGH, the SDO pin is in a high
impedancestate.Duringtheconversionandsleepperiods,
this pin is used as the conversion status output. When
the conversion is in progress this pin is HIGH; once the
conversion is complete SDO goes low. The conversion
status is monitored by pulling CS LOW.
GND(Pin6):Ground.Connectthispintoacommonground
plane through a low impedance connection.
COM (Pin 7): The common negative input (IN–) for all
single ended multiplexer configurations. The voltage on
CH0 to CH3 and COM pins can have any value between
GND – 0.3V to VCC + 0.3V. Within these limits, the two
selected inputs (IN+ and IN–) provide a bipolar input range
(VIN = IN+ – IN–) from –0.5 VREF to 0.5 VREF. Outside
thisinputrange,theconverterproducesuniqueover-range
and under-range output codes.
CH0 to CH3 (Pins 8-11): Analog Inputs. May be pro-
grammed for single-ended or differential mode.
VCC(Pin12):PositiveSupplyVoltage.BypasstoGNDwith
a 10F tantalum capacitor in parallel with a 0.1F ceramic
capacitor as close to the part as possible.
REF+(Pin13),REF–(Pin14):DifferentialReferenceInput.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
remains more positive than the negative reference input,
REF–, by at least 0.1V. The differential voltage (VREF=REF+
– REF–) sets the fullscale range for all input channels.
Exposed Pad (Pin 15): Ground. This pin is ground and
mustbesolderedtothePCBgroundplane.Forprototyping
purposes, this pin may remain floating.
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