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參數(shù)資料
| 型號： | LTC2486CDE#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 4-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC14 |
| 封裝： | 4 X 3 MM, PLASTIC, MO-229WGED-3, QFN-14 |
| 文件頁數(shù)： | 9/36頁 |
| 文件大小： | 659K |
| 代理商： | LTC2486CDE#TR |
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LTC2486
2486fa
applicaTions inFormaTion
+FS. If both Bit 21 and Bit 20 are LOW, the differential
input voltage is below –FS. The function of these bits is
summarized in Table 1.
Table 1. LTC2486 Status Bits
Input Range
Bit 23
EOC
Bit 22
DMY
Bit 21
SIG
Bit 20
MSB
VIN ≥ 0.5 VREF/Gain
0
1
0V ≤ VIN < 0.5 VREF/Gain
0
1
0
–0.5 VREF/Gain ≤ VIN < 0V
0
1
VIN < –0.5 VREF/Gain
0
Bits 20 to 4 are the 16-bit plus sign conversion result
MSB first.
Bit 4 is the least significant bit (LSB16).
Bits 3 to 0 are always LOW.
Data is shifted out of the SDO pin under control of the
serial clock (SCk) (see Figure 3). Whenever CS is HIGH,
SDO remains high impedance and SCk is ignored.
In order to shift the conversion result out of the device,
CS must first be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes in real
time as a function of the internal oscillator or the clock
applied to the fO pin from HIGH to LOW at the completion
of a conversion. This signal may be used as an interrupt for
an external microcontroller. Bit 23 (EOC) can be captured
on the first rising edge of SCk. Bit 22 is shifted out of the
device on the first falling edge of SCk. The final data bit
(Bit 0) is shifted out on the on the falling edge of the 23rd
SCk and may be latched on the rising edge of the 24th SCk
pulse. On the falling edge of the 24th SCk pulse, SDO goes
HIGH indicating the initiation of a new conversion cycle.
This bit serves as EOC (Bit 23) for the next conversion
cycle. Table 2 summarizes the output data format.
As long as the voltage on the IN+ and IN– pins remains
between –0.3V and VCC + 0.3V (absolute maximum op-
erating range) a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 VREF/Gain
to +FS = 0.5 VREF/Gain. For differential input voltages
greater than +FS, the conversion result is clamped to the
value corresponding to +FS + 1LSB. For differential input
voltages below –FS, the conversion result is clamped to
the value –FS – 1LSB.
INPUT DATA FORMAT
TheLTC2486serialinputwordis16bitslongandcontains
two distinct sets of data. The first set (SGL, ODD, A2,
A1, A0) is used to select the input channel. The second
set of data (IM, FA, FB, SPD, GS2, GS1, GS0) is used
to select the frequency rejection, speed mode (1x, 2x),
temperature measurement, and gain.
After power up, the device initiates an internal reset cycle
which sets the input channel to CH0-CH1 (IN+ = CH0, IN– =
CH1),thefrequencyrejectiontosimultaneous50Hz/60Hz,
1xoutputrate(auto-calibrationenabled),andgain=1.The
firstconversionautomaticallybeginsatpowerupusingthis
default configuration. Once the conversion is complete, a
new word may be written into the device.
Figure 3. Channel Selection, Configuration Selection and Data Output Timing
EOC
CS
SCK
(EXTERNAL)
SDI
SDO
2486 F03
CONVERSION
SLEEP
DATA INPUT/OUTPUT
MSB
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11
SIG
BIT 21
“0”
BIT 22
BIT 23
1
0
EN
SGL
A2
A1
A0
EN2
IM
FA
FB
SPD
GS2
GS1
GS0
ODD
BIT 10 BIT 9
BIT 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
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