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參數(shù)資料
| 型號： | LTC2486CDE#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 4-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQCC14 |
| 封裝： | 4 X 3 MM, PLASTIC, MO-229WGED-3, QFN-14 |
| 文件頁數(shù)： | 19/36頁 |
| 文件大?。?/td> | 659K |
| 代理商： | LTC2486CDE#TR |
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LTC2486
2486fa
applicaTions inFormaTion
Figure 11. Internal Serial Clock, Continuous Operation
The input data is shifted through the SDI pin on the ris-
ing edge of SCk (including the first rising edge) and the
output data is shifted out the SDO pin on the falling edge
of SCk. The data input/output cycle is concluded and a
new conversion automatically begins after the 24th rising
edge of SCk. During the next conversion, SCk and SDO
remain HIGH until the conversion is complete.
The Use of a 10k Pull-Up on SCK for Internal SCK
Selection
If CS is pulled HIGH while the converter is driving SCk
LOW, the internal pull-up is not available to restore SCk
to a logic HIGH state if SCk is floating. This will cause the
device to exit the internal SCk mode on the next falling
edge of CS. This can be avoided by adding an external 10k
pull-up resistor to the SCk pin.
Whenever SCk is LOW, the LTC2486’s internal pull-up at
SCk is disabled. Normally, SCk is not externally driven if
the device is operating in the internal SCk timing mode.
However, certain applications may require an external
EOC
CS
SCK
(INTERNAL)
SDI
SDO
2486 F11
CONVERSION
DATA INPUT/OUTPUT
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11
BIT 21
BIT 22
BIT 23
1
0
EN
SGL
A2
A1
A0
EN2
IM
FA
FB
SPD
GS2
GS1
GS0
ODD
BIT 10 BIT 9
BIT 0
2
3
1
4
5
6
7
8
9
10
11
12
13
14
15
16
24
DON'T CARE
MSB
SIG
“0”
VCC
FO
SCK
SDI
SDO
CS
GND
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2486
3-WIRE
SPI INTERFACE
OPTIONAL
10k
VCC
REF+
REF–
CH0
CH1
CH2
CH3
COM
12
1
13
14
8
9
10
11
7
3
5
6
4
2
2.7V TO 5.5V
0.1
F
10
F
CONVERSION
driver on SCk. If the driver goes Hi-Z after outputting a
LOW signal, the internal pull-up is disabled. An external
10k pull-up resistor prevents the device from exiting the
internal SCk mode under this condition.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCk will go LOW. If CS goes HIGH before the time tEOCtest,
the internal pull-up is activated. If SCk is heavily loaded,
the internal pull-up may not restore SCk to a HIGH state
before the next falling edge of CS. The external 10k pull-up
resistor prevents the device from exiting the internal SCk
mode under this condition.
PRESERVING THE CONVERTER ACCURACY
The LTC2486 is designed to reduce as much as possible
sensitivity to device decoupling, PCB layout, anti-aliasing
circuits, line frequency perturbations, and temperature
sensitivity. In order to achieve maximum performance a
few simple precautions should be observed.
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