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參數(shù)資料
| 型號： | LTC2486CDE#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/36頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT W/PGA 14-DFN |
| 標(biāo)準(zhǔn)包裝： | 91 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 15 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 800µW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 14-DFN-EP（4x3） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個單端，雙極；2 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 配用： | DC1009A-C-ND - BOARD DELTA SIGMA ADC LTC2486 |
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LTC2486
13
2486fd
APPLICATIONS INFORMATION
CONVERTER OPERATION
Converter Operation Cycle
The LTC2486 is a multi-channel, low power, delta-sigma,
analog-to-digital converter with an easy-to-use, 4-wire
interface and automatic differential input current cancella-
tion. Its operation is made up of four states (See Figure 2).
The converter operating cycle begins with the conversion,
followed by the sleep state, and ends with the data input/
output cycle. The 4-wire interface consists of serial data
output (SDO), serial clock (SCK), chip select (CS) and
serial data input (SDI).The interface, timing, operation
cycle, and data output format is compatible with Linear’s
entire family of SPI ΔΣ converters.
Initially, at power up, the LTC2486 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in this sleep state, if CS is HIGH, power
consumption is reduced by two orders of magnitude. The
part remains in the sleep state as long as CS is HIGH. The
conversion result is held indenitely in a static shift register
while the part is in the sleep state.
Once CS is pulled LOW, the device powers up, exits the
sleep state, and enters the data input/output state. If CS
is brought HIGH before the rst rising edge of SCK, the
device returns to the sleep state and the power is reduced.
If CS is brought HIGH after the rst rising edge of SCK, the
data output cycle is aborted and a new conversion cycle
begins. The data output corresponds to the conversion
just completed. This result is shifted out on the serial
data output pin (SDO) under the control of the serial
clock pin (SCK). Data is updated on the falling edge of
SCK allowing the user to reliably latch data on the rising
edge of SCK (See Figure 3). The conguration data for
the next conversion is also loaded into the device at this
time. Data is loaded from the serial data input pin (SDI)
on each rising edge of SCK. The data input/output cycle
concludes once 24 bits are read out of the ADC or when
CS is brought HIGH. The device automatically initiates a
new conversion and the cycle repeats.
Through timing control of the CS and SCK pins, the LTC2486
offers several exible modes of operation (internal or
external SCK and free-running conversion modes). These
various modes do not require programming and do not
disturb the cyclic operation described above. These modes
of operation are described in detail in the Serial Interface
Timing Modes section.
Ease of Use
The LTC2486 data output has no latency, lter settling
delay, or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog inputs is straightforward. Each conver-
sion, immediately following a newly selected input or
mode, is valid and accurate to the full specications of
the device.
The LTC2486 automatically performs offset and full scale
calibration every conversion cycle independent of the
input channel selected. This calibration is transparent to
the user and has no effect with the operation cycle de-
scribed above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with
respect to time, supply voltage variation, input channel,
and temperature drift.
Figure 2. LTC2486 State Transition Diagram
CONVERT
SLEEP
CHANNEL SELECT
CONFIGURATION SELECT
DATA OUTPUT
POWER UP
IN+= CH0, IN–= CH1
50/60Hz, GAIN = 1, 1X
2486 F02
CS = LOW
AND
SCK
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