參數(shù)資料
型號(hào)： LTC2482CDD#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 16/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT 10-DFN
標(biāo)準(zhǔn)包裝： 121
位數(shù)： 16
采樣率（每秒）： 6.8
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 480µW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 10-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 10-DFN（3x3）
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)差分，雙極
產(chǎn)品目錄頁(yè)面： 1348 (CN2011-ZH PDF)
配用： DC941A-ND - BOARD DELTA SIGMA ADC LTC2482
LTC2482
23
2482fc
APPLICATIONS INFORMATION
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specication can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN+ and
IN–, the expected drift of the dynamic current and offset
will be insignicant (about 1% of their respective values
over the entire temperature and voltage range). Even for
the most stringent applications, a one-time calibration
operation may be sufcient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 1k source resistance will create a
1μV typical and 10μV maximum offset voltage.
Reference Current
In a similar fashion, the LTC2482 samples the differential
reference pins VREF+ and GND transferring small amount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can
be analyzed in two distinct situations.
For relatively small values of the external reference capaci-
tors (CREF < 1nF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gain performance without signicant benets of reference
ltering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 1nF) may be
required as reference lters in certain congurations. Such
capacitors will average the reference sampling charge and
the external source resistance will see a quasi constant
reference differential impedance.
In the following discussion, it is assumed the input and
reference common mode are the same. Using internal
oscillator (50Hz/60Hz rejection), the differential reference
CIN
2482 F11
VINCM + 0.5VIN
RSOURCE
IN+
LTC2482
CPAR
20pF
CIN
VINCM – 0.5VIN
RSOURCE
IN–
CPAR
20pF
Figure 11. An RC Network at IN+ and IN–
RSOURCE (Ω)
1
+FS
ERROR
(ppm)
–20
0
20
1k
100k
2482 F12
–40
–60
–80
10
100
10k
40
60
80
VCC = 5V
VREF = 5V
VIN
+ = 3.75V
VIN
– = 1.25V
fO = GND
TA = 25°C
CIN = 0pF
CIN = 100pF
CIN = 1nF, 0.1μF, 1μF
Figure 12. +FS Error vs RSOURCE at IN+ and IN–
RSOURCE (Ω)
1
–FS
ERROR
(ppm)
–20
0
20
1k
100k
2482 F13
–40
–60
–80
10
100
10k
40
60
80
VCC = 5V
VREF = 5V
VIN
+ = 1.25V
VIN
– = 3.75V
fO = GND
TA = 25°C
CIN = 0pF
CIN = 100pF
CIN = 1nF, 0.1μF, 1μF
Figure 13. –FS Error vs RSOURCE at IN+ and IN–
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