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參數(shù)資料
| 型號： | LTC2481HDD#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 20/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT I2C 7.5SPS 10DFN |
| 標(biāo)準(zhǔn)包裝： | 121 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | I²C，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 480µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 10-DFN（3x3） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，雙極；1 個(gè)差分，雙極 |
| 配用： | DC951A-ND - BOARD DELTA SIGMA ADC LTC2481 |
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LTC2481
27
2481fc
APPLICATIONS INFORMATION
Output Data Rate
When using its internal oscillator, the LTC2481 produces up
to 7.5 samples per second (sps) with a notch frequency of
60Hz, 6.25sps with a notch frequency of 50Hz and 6.82sps
with the 50Hz/60Hz rejection mode. The actual output
data rate will depend upon the length of the sleep and
data output phases which are controlled by the user and
which can be made insignicantly short. When operated
with an external conversion clock (CA0/f0 connected to
an external oscillator), the LTC2481 output data rate can
be increased as desired. The duration of the conversion
phase is 41036/fEOSC. If fEOSC = 307.2kHz, the converter
behaves as if the internal oscillator is used and the notch
is set at 60Hz.
An increase in fEOSC over the nominal 307.2kHz will
translate into a proportional increase in the maximum
output data rate. The increase in output rate is neverthe-
less accompanied by three potential effects, which must
be carefully considered.
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line fre-
quency. In many applications, the subsequent performance
degradation can be substantially reduced by relying upon
the LTC2481’s exceptional common mode rejection and by
carefully eliminating common mode to differential mode
conversion sources in the input circuit. The user should
avoid single-ended input lters and should maintain a
very high degree of matching and symmetry in the circuits
driving the IN+ and IN– pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (CIN, CREF) are used, the
previous section provides formulae for evaluating the effect
of the source resistance upon the converter performance for
any value of fEOSC. If small external input and/or reference
capacitors (CIN, CREF) are used, the effect of the external
source resistance upon the LTC2481 typical performance
can be inferred from Figures 14, 15, 16 and 17 in which
the horizontal axis is scaled by 307200/fEOSC.
Third, an increase in the frequency of the external oscillator
above 1MHz (a more than 3x increase in the output data
rate) will start to decrease the effectiveness of the internal
autocalibration circuits. This will result in a progressive
degradation in the converter accuracy and linearity. Typical
measured performance curves for output data rates up to
100 readings per second are shown in Figures 21 to 28. In
order to obtain the highest possible level of accuracy from
this converter at output data rates above 20 readings per
second, the user is advised to maximize the power supply
voltage used and to limit the maximum ambient operating
temperature. In certain circumstances, a reduction of the
differential reference voltage may be benecial.
Input Bandwidth
The combined effect of the internal SINC4 digital lter and
of the analog and digital autocalibration circuits determines
the LTC2481 input bandwidth. When the internal oscillator
is used with the notch set at 60Hz, the 3dB input bandwidth
is 3.63Hz. When the internal oscillator is used with the
notch set at 50Hz, the 3dB input bandwidth is 3.02Hz. If
an external conversion clock generator of frequency fEOSC
is connected to the CA0/f0 pin, the 3dB input bandwidth
is 11.8 10–6 fEOSC.
Due to the complex ltering and calibration algorithms
utilized, the converter input bandwidth is not modeled
very accurately by a rst order lter with the pole located
at the 3dB frequency. When the internal oscillator is used,
the shape of the LTC2481 input bandwidth is shown in
Figure 29. When an external oscillator of frequency fEOSC
is used, the shape of the LTC2481 input bandwidth can
be derived from Figure 29, 60Hz mode curve in which
the horizontal axis is scaled by fEOSC/307200.
The conversion noise (600nVRMS typical for VREF = 5V)
can be modeled by a white noise source connected to a
noise free converter. The noise spectral density is 47nV√Hz
for an innite bandwidth source and 64nV√Hz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplication circuits. Such circuits face the simultaneous
requirements of very low bandwidth (just a few Hz) in
order to reduce the output referred noise and relatively
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