參數(shù)資料
型號(hào)： LTC2481HDD#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 19/40頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT I2C 7.5SPS 10DFN
標(biāo)準(zhǔn)包裝： 121
位數(shù)： 16
采樣率（每秒）： 7.5
數(shù)據(jù)接口： I²C，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 480µW
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 10-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 10-DFN（3x3）
包裝： 管件
輸入數(shù)目和類型： 2 個(gè)單端，雙極；1 個(gè)差分，雙極
配用： DC951A-ND - BOARD DELTA SIGMA ADC LTC2481
LTC2481
26
2481fc
APPLICATIONS INFORMATION
In applications where the reference and input common
mode voltages are different, extra errors are introduced.
For every 1V of the reference and input common mode
voltage difference (VREFCM – VINCM) and a 5V reference,
each Ohm of reference source resistance introduces an
extra (VREFCM – VINCM)/(VREF REQ) full-scale gain error,
which is 0.074ppm when using internal oscillator and 60Hz
mode. When using internal oscillator and 50Hz/60Hz mode,
the extra full-scale gain error is 0.067ppm. When using
internal oscillator and 50Hz mode, the extra gain error is
0.061ppm. If an external clock is used, the corresponding
extra gain error is 0.24 10–6 fEOSCppm.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors
and upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
Figure 21. Offset Error vs Output Data Rate and Temperature
Figure 22. +FS Error vs Output Data Rate and Temperature
OUTPUT DATA RATE (READINGS/SEC)
–10
OFFSET
ERROR
(ppm
OF
V
REF
)
10
30
50
0
20
40
20
40
60
80
2481 F21
100
10
030
50
70
90
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
CA0/f0 = EXT CLOCK
TA = 85°C
TA = 25°C
OUTPUT DATA RATE (READINGS/SEC)
0
+FS
ERROR
(ppm
OF
V
REF
)
500
1500
2000
2500
3500
10
50
70
2481 F22
1000
3000
40
90 100
20 30
60
80
VIN(CM) = VREF(CM)
VCC = VREF = 5V
CA0/f0 = EXT CLOCK
TA = 85°C
TA = 25°C
Figure 23. –FS Error vs Output Data Rate and Temperature
OUTPUT DATA RATE (READINGS/SEC)
0
–3500
–FS
ERROR
(ppm
OF
V
REF
)
–3000
–2000
–1500
–1000
0
10
50
70
2481 F23
–2500
–500
40
90 100
20 30
60
80
VIN(CM) = VREF(CM)
VCC = VREF = 5V
CA0/f0 = EXT CLOCK
TA = 85°C
TA = 25°C
Figure 20. INL vs DIFFERENTIAL Input Voltage and
Reference Source Resistance for CREF > 1μF
VIN/VREF (V)
–0.5
INL
(ppm
OF
V
REF
)
2
6
10
0.3
2481 F20
–2
–6
0
4
8
–4
–8
–10
–0.3
–0.1
0.1
0.5
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
CREF = 10μF
R = 1k
R = 100Ω
R = 500Ω
and power supply range is typically better than 0.5%. Such
a specication can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by VREF+
and VREF–, the expected drift of the dynamic current gain
error will be insignicant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications a one-time calibration operation
may be sufcient.
In addition to the reference sampling charge, the refer-
ence pins ESD protection diodes have a temperature de-
pendent leakage current. This leakage current, nominally
1nA (±100nA max), results in a small gain error. A 100Ω
source resistance will create a 0.05μV typical and 5μV
maximum full-scale error.
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