參數(shù)資料
型號： LTC2480IMS#PBF
廠商： Linear Technology
文件頁數(shù)： 26/42頁
文件大?。?/td> 0K
描述： IC ADC 16BIT 10-MSOP
標(biāo)準(zhǔn)包裝： 50
位數(shù)： 16
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 管件
輸入數(shù)目和類型： 2 個單端，雙極；1 個差分，雙極
配用： DC798B-ND - BOARD DELTA SIGMA ADC LTC2480
LTC2480
2480fd
applicaTions inForMaTion
internal oscillator and 50Hz mode, the extra gain error is
0.061ppm. If an external clock is used, the corresponding
extra gain error is 0.24 10–6 fEOSCppm.
The magnitude of the dynamic reference current depends
uponthesizeoftheverystableinternalsamplingcapacitors
andupontheaccuracyoftheconvertersamplingclock.The
accuracy of the internal clock over the entire temperature
andpowersupplyrangeistypicallybetterthan0.5%.Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by VREF+
and GND, the expected drift of the dynamic current gain
error will be insignificant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications a one-time calibration operation
may be sufficient.
In addition to the reference sampling charge, the refer-
ence pins ESD protection diodes have a temperature
dependentleakagecurrent.Thisleakagecurrent,nominally
1nA (±10nA max), results in a small gain error. A 100Ω
source resistance will create a 0.05V typical and 0.5V
maximum full-scale error.
OUTPUT DATA RATE (READINGS/SEC)
–10
OFFSET
ERROR
(ppm
OF
V
REF
)
10
30
50
0
20
40
20
40
60
80
2480 F20
100
10
0
30
50
70
90
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
FO = EXT CLOCK
TA = 85°C
TA = 25°C
Figure 20. Offset Error vs Output Data
Rate and Temperature
OUTPUT DATA RATE (READINGS/SEC)
0
+FS
ERROR
(ppm
OF
V
REF
)
500
1500
2000
2500
3500
10
50
70
2480 F21
1000
3000
40
90 100
20 30
60
80
VIN(CM) = VREF(CM)
VCC = VREF = 5V
FO = EXT CLOCK
TA = 85°C
TA = 25°C
OUTPUT DATA RATE (READINGS/SEC)
0
–3500
–FS
ERROR
(ppm
OF
V
REF
)
–3000
–2000
–1500
–1000
0
10
50
70
2480 F22
–2500
–500
40
90 100
20 30
60
80
VIN(CM) = VREF(CM)
VCC = VREF = 5V
FO = EXT CLOCK
TA = 85°C
TA = 25°C
Figure 22. –FS Error vs Output Data
Rate and Temperature
Figure 21. +FS Error vs Output Data
Rate and Temperature
Output Data Rate
When using its internal oscillator, the LTC2480 produces
up to 7.5 samples per second (sps) with a notch frequency
of 60Hz, 6.25sps with a notch frequency of 50Hz and
6.82sps with the 50Hz/60Hz rejection mode. The actual
output data rate will depend upon the length of the sleep
and data output phases which are controlled by the user
and which can be made insignificantly short. When oper-
ated with an external conversion clock (fO connected to
an external oscillator), the LTC2480 output data rate can
be increased as desired. The duration of the conversion
phase is 41036/fEOSC. If fEOSC = 307.2kHz, the converter
behaves as if the internal oscillator is used and the notch
is set at 60Hz.
An increase in fEOSC over the nominal 307.2kHz will
translate into a proportional increase in the maximum
output data rate. The increase in output rate is neverthe-
less accompanied by three potential effects, which must
be carefully considered.
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line fre-
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