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參數(shù)資料
| 型號： | LTC2480CMS |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | PLASTIC, MSOP-10 |
| 文件頁數(shù)： | 8/40頁 |
| 文件大?。?/td> | 601K |
| 代理商： | LTC2480CMS |
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16
LTC2480
2480fa
Output Data Format
The LTC2480 serial output data stream is 24 bits long. The
first 3 bits represent status information indicating the sign
and conversion state. The next 17 bits are the conversion
result, MSB first. The remaining 4 bits indicate the con-
figuration state associated with the current conversion
result. The third and fourth bit together are also used to
indicate an underrange condition (the differential input
voltage is below –FS) or an overrange condition (the
differential input voltage is above +FS).
In applications where the processor generates 32 clock
cycles, or to remain compatible with higher resolution
converters, the LTC2480’s digital interface will ignore
extra clock edges seen during the next conversion period
after the 24th and output “1” for the extra clock cycles.
Furthermore, CS may be pulled high prior to outputting all
24 bits, aborting the data out transfer and initiating a new
conversion.
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 21 (third output bit) is the conversion result sign indi-
cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this
bit is LOW.
Bit 20 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 21 also
provides the underrange or overrange indication. If both
Bit 21 and Bit 20 are HIGH, the differential input voltage is
above +FS. If both Bit 21 and Bit 20 are LOW, the
differential input voltage is below –FS.
The function of these bits is summarized in Table 3.
Table 3. LTC2480 Status Bits
BIT 23 BIT 22 BIT 21 BIT 20
INPUT RANGE
EOC
DMY
SIG
MSB
VIN ≥ 0.5 VREF
0011
0V
≤ VIN < 0.5 VREF
0010
–0.5 VREF ≤ VIN < 0V
0001
VIN < – 0.5 VREF
0000
Bits 20-4 are the 16-bit plus sign conversion result MSB
first.
Bits 3-0 are the corresponding configuration bits for the
present conversion result. Bits 3-1 are the gain set bits and
bit 0 is IM (see Figure 2).
Data is shifted out of the SDO pin under control of the serial
clock (SCK) (see Figure 2). Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes in real time
APPLICATIO S I FOR ATIO
WU
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Table 4. LTC2480 Output Data Format
DIFFERENTIAL INPUT VOLTAGE
BIT 23
BIT 22
BIT 21
BIT 20
BIT 19
BIT 18
BIT 17
…
BIT 4
VIN*
EOC
DMY
SIG
MSB
VIN* ≥ FS**
0
0110
0
…
0
FS** – 1LSB
0
0101
1
…
1
0.5 FS**
0
0101
0
…
0
0.5 FS** – 1LSB
0
0100
1
…
1
0
0100
0
…
0
–1LSB
0
0011
1
…
1
– 0.5 FS**
0
0011
0
…
0
– 0.5 FS** – 1LSB
0
0010
1
…
1
– FS**
0
0010
0
…
0
VIN* < –FS**
0
0001
1
…
1
*The differential input voltage VIN = IN+ – IN–. **The full-scale voltage FS = 0.5 VREF/GAIN.
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