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參數(shù)資料
| 型號： | LTC2480CMS#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | PLASTIC, MSOP-10 |
| 文件頁數(shù)： | 9/40頁 |
| 文件大?。?/td> | 601K |
| 代理商： | LTC2480CMS#TR |
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LTC2480
2480fa
from HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external
microcontroller. Bit 23 (EOC) can be captured on the first
rising edge of SCK. Bit 22 is shifted out of the device on the
first falling edge of SCK. The final data bit (Bit 0) is shifted
out on the falling edge of the 23rd SCK and may be latched
on the rising edge of the 24th SCK pulse. On the falling
edge of the 24th SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 23) for the next conversion cycle. Table 4 summarizes
the output data format.
As long as the voltage on the IN+ and IN– pins is maintained
within the – 0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 VREF/GAIN
to +FS = 0.5 VREF/GAIN. For differential input voltages
greater than +FS, the conversion result is clamped to the
value corresponding to the +FS + 1LSB. For differential
input voltages below –FS, the conversion result is clamped
to the value corresponding to –FS – 1LSB.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a SINC or Comb filter). For high
resolution, low frequency applications, this filter is typically
designed to reject line frequencies of 50Hz or 60Hz plus their
harmonics. The filter rejection performance is directly re-
lated to the accuracy of the converter system clock. The
LTC2480 incorporates a highly accurate on-chip oscillator.
This eliminates the need for external frequency setting com-
ponents such as crystals or oscillators.
Frequency Rejection Selection (FO)
The LTC2480 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and all its
harmonics (up to the 255th) for 50Hz
±2% or 60Hz ±2%,
or better than 87dB normal mode rejection from 48Hz to
62.4Hz. The rejection mode is selected by writing to the
on-chip configuration register and the default mode at
POR is simultaneous 50Hz/60Hz rejection.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2480 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the FO pin and turns off the internal oscillator. The
frequency fEOSC of the external signal must be at least
10kHz to be detected. The external clock signal duty cycle
is not significant as long as the minimum and maximum
specifications for the high and low periods tHEO and tLEO
are observed.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2480 provides better than 110dB
normal mode rejection in a frequency range of fEOSC/5120
±4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from fEOSC/5120
is shown in Figure 3.
Whenever an external clock is not present at the FO pin, the
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2480
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
not be affected. If the change occurs during the data output
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.
APPLICATIO S I FOR ATIO
WU
UU
Figure 3. LTC2480 Normal Mode Rejection When Using
an External Oscillator
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC/5120(%)
–12
–8
–4
0
4
8
12
NORMAL
MODE
REJECTION
(dB)
2480 F03
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
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