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參數資料
| 型號： | LTC2480CMS#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | PLASTIC, MSOP-10 |
| 文件頁數： | 21/40頁 |
| 文件大?。?/td> | 601K |
| 代理商： | LTC2480CMS#TR |
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28
LTC2480
2480fa
APPLICATIO S I FOR ATIO
WU
UU
Figure 12. An RC Network at IN+ and IN–
Figure 13. +FS Error vs RSOURCE at IN+ or IN–
Figure 14. –FS Error vs RSOURCE at IN+ or IN–
CEXT
2480 F12
VINCM + 0.5VIN
RSOURCE
IN+
LTC2480
CPAR
20pF
CEXT
VINCM – 0.5VIN
RSOURCE
IN –
CPAR
20pF
RSOURCE ()
1
+FS
ERROR
(ppm)
–20
0
20
1k
100k
2480 F13
–40
–60
–80
10
100
10k
40
60
80
VCC = 5V
VREF = 5V
VIN
+ = 3.75V
VIN
– = 1.25V
FO = GND
TA = 25°C
CEXT = 0pF
CEXT = 100pF
CEXT = 1nF, 0.1F, 1F
RSOURCE ()
1
–
FS
ERROR
(ppm)
–20
0
20
1k
100k
2480 F14
–40
–60
–80
10
100
10k
40
60
80
VCC = 5V
VREF = 5V
VIN
+ = 1.25V
VIN
– = 3.75V
FO = GND
TA = 25°C
CEXT = 0pF
CEXT = 100pF
CEXT = 1nF, 0.1F, 1F
common mode input current varies proportionally with
input voltage. For the case of balanced input impedances,
the common mode input current effects are rejected by the
large CMRR of the LTC2480 leading to little degradation in
accuracy. Mismatches in source impedances lead to gain
errors proportional to the difference between the common
mode input voltage and the common mode reference
voltage. 1% mismatches in 1k
source resistances lead
to worst-case gain errors on the order of 15ppm or 1LSB
(for 1V differences in reference and input common mode
voltage). Table 7 summarizes the effects of mismatched
source impedance and differences in reference/input com-
mon mode voltages.
Table 7. Suggested Input Configuration for LTC2480
BALANCED INPUT
UNBALANCED INPUT
RESISTANCES
Constant
CEXT > 1nF at Both
CEXT > 1nF at Both IN+
VIN(CM) – VREF(CM) IN
+ and IN–. Can Take
and IN–. Can Take Large
Large Source Resistance
Source Resistance.
with Negligible Error
Unbalanced Resistance
Results in an Offset
Which Can be Calibrated
Varying
CEXT > 1nF at Both IN+
Minimize IN+ and IN–
VIN(CM) – VREF(CM) and IN–. Can Take Large
Capacitors and Avoid
Source Resistance with
Large Source Impedance
Negligible Error
(< 5k Recommended)
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/
°C) are
used for the external source impedance seen by IN+ and
IN–, the expected drift of the dynamic current and offset
will be insignificant (about 1% of their respective values
over the entire temperature and voltage range). Even for
the most stringent applications, a one-time calibration
operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (
±10nA max), results
in a small offset shift. A 1k source resistance will create a
1
V typical and 10V maximum offset voltage.
In applications where the common mode input voltage
varies as a function of input signal level (single-ended
input, RTDs, half bridges, current sensors, etc.), the
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