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參數(shù)資料
| 型號(hào)： | LTC2451CTS8 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | PLASTIC, MO-193, TSOT-23, 8 PIN |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 221K |
| 代理商： | LTC2451CTS8 |
LTC2451
10
2451fd
conversion speed. The default conversion speed is 60Hz.
The user can specify a 30Hz conversion speed by setting
the eighth bit (S30) = 1, or specify a 60Hz conversion
speed by setting the eighth bit (S30) = 0.
After a Read request and an ACK, the LTC2451 can output
data, as shown in Figure 4. The data output stream is 16
bits long and is shifted out on the falling edges of SCL. The
rst bit is the MSB (D15) and is followed by successively
less signicant bits (D14, D13 ...) until the LSB (D0) is
output by the LTC2451. This sequence is summarized in
Figure 5.
OPERATION SEQUENCE
Continuous Read
Conversions from the LTC2451 can be continuously read
(see Figure 7). At the end of a Read operation, a new
conversion automatically begins. At the conclusion of
the conversion cycle, the next result may be read using
the method described above. If the conversion cycle is
not concluded and a valid address selects the device, the
LTC2451 generates a NAK signal indicating the conversion
cycle is in progress.
Figure 3. Timing Diagram for Write Sequence
APPLICATIONS INFORMATION
Figure 4. Timing Diagram for Read Sequence
Figure 5. Conversion Sequence
1
789
2
3
14
S30
W
SDA
SCL
7-BIT
ADDRESS
START BY
MASTER
S30 = 1: 30Hz MODE
S30 = 0: 60Hz MODE
56
7
8
9
ACK BY
LTC2451
SLEEP
DATA INPUT
2451 F03
ACK BY
MASTER
17
8
9
2
3
18
D8
D13
D14
MSB
D15
R
SDA
SCL
7-BIT
ADDRESS
START BY
MASTER
D7
D6
D5
D0
LSB
91
2
3
8
9
ACK BY
LTC2451
ACK BY
MASTER
NACK BY
MASTER
SLEEP
DATA OUTPUT
CONVERT
2451 F04
SLEEP
7-BIT ADDRESS
(0010100)
SP
R
ACK
READ
DATA OUTPUT
CONVERSION
2451 F05
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