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參數(shù)資料
| 型號： | LTC2451CTS8 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | PLASTIC, MO-193, TSOT-23, 8 PIN |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 221K |
| 代理商： | LTC2451CTS8 |
LTC2451
7
2451fd
BLOCK DIAGRAM
PIN FUNCTIONS
GND (Pin 1, 5): Ground. Connect to a ground plane through
a low impedance connection.
REF– (Pin 2), REF+ (Pin 3):
Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
remains more positive than the negative reference input,
REF–, by at least 2.5V. The differential reference voltage
(VREF = REF+ to REF–) sets the full-scale range.
VCC (Pin 4): Positive Supply Voltage. Bypass to GND
(Pin 1) with a 10μF capacitor in parallel with a low series
inductance 0.1μF capacitor located as close to the part
as possible.
IN (Pin 6): Analog Input. IN’s single-ended input range
is VREF– to VREF+.
SCL (Pin 7): Serial Clock Input of the I2C Interface. The
LTC2451 can only act as a slave and the SCL pin only
accepts an external serial clock. Data is shifted into the
SDA pin on the rising edges of SCL and output through
the SDA pin on the falling edges of SCL.
SDA (Pin 8): Bidirectional Serial Data Line of the I2C In-
terface. The conversion result is output through the SDA
pin. The pin is high impedance unless the LTC2451 is in
the data output mode. While the LTC2451 is in the data
output mode, SDA is an open-drain pull-down (which
requires an external 1.7k pull-up resistor to VCC).
Exposed Pad (Pin 9): Ground. Must be soldered to PCB
ground.
16-BIT Δ∑
A/D CONVERTER
SCL
REF+
VCC
REF–
IN
SDA
2451 BD
I2C
INTERFACE
INTERNAL
OSCILLATOR
3
4
7
8
GND
1, 5, 9
1
2
6
APPLICATIONS INFORMATION
CONVERTER OPERATION
Converter Operation Cycle
The LTC2451 is a low power, delta-sigma analog-to-
digital converter with an I2C interface. Its operation, as
shown in Figure 1, is composed of three successive states:
conversion, sleep, and data input/output.
Initially, at power-up, the LTC2451 is set to its default 60Hz
mode and performs a conversion. Once the conversion is
complete, the device enters the sleep state. While in the
sleep state, power consumption is reduced by several
orders of magnitude. The part remains in the sleep state
as long it is not addressed for a Read or Write operation.
The conversion result is held indenitely in a static shift
register while the part is in the sleep state.
The device will not acknowledge an external request dur-
ing the conversion state. After a conversion is nished,
the device is ready to accept a Read/Write request. The
LTC2451’s address is hardwired at 0010100. Once the
LTC2451 is addressed for a Read operation, the device
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