Larger values of reference capacitors (CREF > 0.01F) may" />
參數(shù)資料
型號(hào)： LTC2433-1CMS#PBF
廠(chǎng)商： Linear Technology
文件頁(yè)數(shù)： 16/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC DIFF 16BIT 3WIRE 10-MSOP
標(biāo)準(zhǔn)包裝： 50
位數(shù)： 16
采樣率（每秒）： 6.8
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 1 個(gè)差分，雙極
產(chǎn)品目錄頁(yè)面： 1348 (CN2011-ZH PDF)
配用： DC745A-ND - BOARD DELTA SIGMA ADC LTC2433-1
LTC2433-1
23
24331fa
Larger values of reference capacitors (CREF > 0.01F) may
be required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi con-
stant reference differential impedance. When FO = LOW
(internal oscillator and 50Hz/60Hz notch), the typical
differential reference resistance is 4.2M
which will gen-
erate a gain error of approximately 1LSB full scale for each
120
of source resistance driving REF+ or REF–. When FO
is driven by an external oscillator with a frequency fEOSC
(external conversion clock operation), the typical differen-
tial reference resistance is 0.60 1012/fEOSC and each
ohm of source resistance drving REF+ or REF– will result
in 5.1 10–8 fEOSCLSB gain error at full scale. The effect
Figure 19. +FS Error vs RSOURCE at REF+ or REF– (Small CIN)
Figure 20. –FS Error vs RSOURCE at REF+ or REF– (Small CIN)
Figure 21. +FS Error vs RSOURCE at REF+ and REF– (Large CREF)
Figure 22. –FS Error vs RSOURCE at REF+ and REF– (Large CREF)
RSOURCE ()
1
10
100
1k
10k
100k
+FS
ERROR
(LSB)
24331 F19
0
–1
–2
–3
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
CREF = 0.01F
CREF = 0.001F
CREF = 100pF
CREF = 0pF
RSOURCE ()
1
10
100
1k
10k
100k
–
FS
ERROR
(LSB)
24331 F20
3
2
1
0
CREF = 0.01F
CREF = 0.001F
CREF = 100pF
CREF = 0pF
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
RSOURCE ()
0
+FS
ERROR
(LSB)
0
–5
–10
800
24331 F21
200
400
600
1000
700
100
300
500
900
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
CREF = 0.01F
CREF = 1F
CREF = 0.1F
CREF = 10F
RSOURCE ()
0
–
FS
ERROR
(LSB)
10
5
0
800
24331 F22
200
400
600
1000
700
100
300
500
900
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
CREF = 0.01F
CREF = 1F
CREF = 0.1F
CREF = 10F
of the source resistance on the two reference pins is
additive with respect to this gain error. The typical +FS and
–FS errors for various combinations of source resistance
seen by the REF+ and REF– pins and external capacitance
CREF connected to these pins are shown in Figures 19, 20,
21 and 22.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
When FO = LOW (internal oscillator and 50Hz/60Hz notch),
every 1000
of source resistance driving REF+ or REF–
translates into about 1LSB additional INL error. When FO
is driven by an external oscillator with a frequency fEOSC,
every 1000
of source resistance driving REF+ or REF–
APPLICATIO S I FOR ATIO
WU
UU
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