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參數(shù)資料
型號： LTC2433-1CMS#PBF
廠商： Linear Technology
文件頁數(shù)： 14/28頁
文件大?。?/td> 0K
描述： IC ADC DIFF 16BIT 3WIRE 10-MSOP
標(biāo)準(zhǔn)包裝： 50
位數(shù)： 16
采樣率（每秒）： 6.8
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 管件
輸入數(shù)目和類型： 1 個差分，雙極
產(chǎn)品目錄頁面： 1348 (CN2011-ZH PDF)
配用： DC745A-ND - BOARD DELTA SIGMA ADC LTC2433-1
LTC2433-1
21
24331fa
by Figures 14 and 15. For simplicity, two distinct situa-
tions can be considered.
For relatively small values of input capacitance (CIN <
0.01
F), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
source impedance result in only small errors. Such values
for CIN will deteriorate the converter offset and gain
performance without significant benefits of signal filtering
and the user is advised to avoid them. Nevertheless, when
small values of CIN are unavoidably present as parasitics
of input multiplexers, wires, connectors or sensors, the
LTC2433-1 can maintain its accuracy while operating with
relative large values of source resistance as shown in
Figure 16. +FS Error vs RSOURCE at IN+ or IN– (Large CIN)
Figure 17. –FS Error vs RSOURCE at IN+ or IN– (Large CIN)
RSOURCE ()
0 100 200 300 400 500 600 700 800 900 1000
+FS
ERROR
(LSB)
24331 F16
8
4
0
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = 3.75V
IN– = 1.25V
FO = GND
TA = 25°C
CIN = 1F
CIN = 0.1F
CIN = 0.01F
CIN = 10F
RSOURCE ()
0 100 200 300 400 500 600 700 800 900 1000
–
FS
ERROR
(ppm
OF
V
REF
)
24331 F17
–8
–4
0
CIN = 0.1F
CIN = 0.01F
CIN = 10F
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = 1.25V
IN– = 3.75V
FO = GND
TA = 25°C
CIN = 1F
Figure 15. –FS Error vs RSOURCE at IN
+ or IN– (Small CIN)
RSOURCE ()
1
10
100
1k
10k
100k
–
FS
ERROR
(LSB)
24331 F15
0
–1
–2
–3
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = GND
IN– = 2.5V
FO = GND
TA = 25°C
CIN = 0pF
CIN = 0.001F
CIN = 100pF
CIN = 0.01F
Figures 14 and 15. These measured results may be slightly
different from the first order approximation suggested
earlier because they include the effect of the actual second
order input network together with the nonlinear settling
process of the input amplifiers. For small CIN values, the
settling on IN+ and IN– occurs almost independently and
there is little benefit in trying to match the source imped-
ance for the two pins.
Larger values of input capacitors (CIN > 0.01F) may be
required in certain configurations for antialiasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When FO = LOW (internal oscillator and 50Hz/60Hz notch),
the typical differential input resistance is 6M
which will
generate a gain error of approximately 1LSB at full scale
for each 180
of source resistance driving IN+ or IN–.
When FO is driven by an external oscillator with a fre-
quency fEOSC (external conversion clock operation), the
typical differential input resistance is 0.84 1012/fEOSC
and each ohm of source resistance driving IN+ or IN– will
result in 3.7 10–8 fEOSCLSB gain error at full scale. The
effect of the source resistance on the two input pins is
additive with respect to this gain error. The typical +FS and
–FS errors as a function of the sum of the source resis-
tance seen by IN+ and IN– for large values of CIN are shown
in Figures 16 and 17.
APPLICATIO S I FOR ATIO
WU
UU
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