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參數(shù)資料
| 型號： | LTC2431IMS#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 20BIT DIFFINPUT/REF10MSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 20 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 1mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 配用： | DC586A-ND - BOARD DELTA SIGMA ADC LTC2431 |
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LTC2430/LTC2431
16
24301f
EOC
BIT 23
SDO
SCK
(EXTERNAL)
CS
TEST EOC
LSB
MSB
SIG
BIT 0
BIT 19
BIT 18
BIT 20
BIT 21
BIT 22
SLEEP
TEST EOC
DATA OUTPUT
CONVERSION
2431 F05
CONVERSION
Hi-Z
TEST EOC
VCC
FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1
F
2.7V TO 5.5V
LTC2430/
LTC2431
3-WIRE
SPI INTERFACE
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
VCC
TEST EOC
Table 4. LTC2430/LTC2431 Interface Timing Modes
Conversion
Data
Connection
SCK
Cycle
Output
and
Configuration
Source
Control
Waveforms
External SCK, Single Cycle Conversion
External
CS and SCK
Figures 5, 6
External SCK, 2-Wire I/O
External
SCK
Figure 7
Internal SCK, Single Cycle Conversion
Internal
CS
↓
CS
↓
Figures 8, 9
Internal SCK, 2-Wire I/O, Continuous Conversion
Internal
Continuous
Internal
Figure 10
The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the conversion is over. With CS HIGH, the device auto-
matically enters the low power sleep state once the con-
version is complete.
When CS is low, the device enters the data output mode.
The result is held in the internal static shift register until
the first SCK rising edge is seen while CS is LOW. Data is
shifted out the SDO pin on each falling edge of SCK. This
enables external circuitry to latch the output on the rising
edge of SCK. EOC can be latched on the first rising edge
of SCK and the last bit of the conversion result can be
latched on the 24th rising edge of SCK. On the 24th falling
edge of SCK, the device begins a new conversion. SDO
goes HIGH (EOC = 1) indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the 24th
falling edge of SCK, see Figure 6. On the rising edge of CS,
APPLICATIO S I FOR ATIO
WU
UU
Figure 5. External Serial Clock, Single Cycle Operation
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