參數(shù)資料
型號(hào)： LTC2411IMS#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 18/40頁(yè)
文件大?。?/td> 0K
描述： IC A/D CONV 24BIT MICRPWR 10MSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 24
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)差分，雙極
LTC2411/LTC2411-1
25
eliminates the offset error caused by mismatched source
impedances.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 1%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/
°C) are
used for the external source impedance seen by IN+ and
IN–, the expected drift of the dynamic current, offset and
gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (
±10nA max), results
in a small offset shift. A 100
source resistance will create
a 0.1
V typical and 1V maximum offset voltage.
Reference Current
In a similar fashion, the LTC2411/LTC2411-1 sample the
differential reference pins REF+ and REF– transfering small
amount of charge to and from the external driving circuits
thus producing a dynamic reference current. This current
does not change the converter offset, but it may degrade
the gain and INL performance. The effect of this current
can be analyzed in the same two distinct situations.
For relatively small values of the external reference capaci-
tors (CREF < 0.01F), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 0.01F)
may be required as reference filters in certain configura-
tions. Such capacitors will average the reference sam-
pling charge and the external source resistance will see a
quasi constant reference differential impedance. For the
LTC2411, when FO = LOW (internal oscillator and 60Hz
notch), the typical differential reference resistance is
3.9M
which will generate a gain error of approximately
0.13ppm for each ohm of source resistance driving REF+
or REF–. When FO = HIGH (internal oscillator and 50Hz
notch), the typical differential reference resistance is
4.68M
whichwillgenerateagainerrorofapproximately
0.11ppm for each ohm of source resistance driving REF+
or REF –. For the LTC2411-1, when internal oscillator is
used (FO = LOW), the typical differential reference resis-
tance is 4.29M
which will generate a gain error of
approximately 0.12ppm for each ohm of source resis-
tance driving REF+ or REF –. When FO is driven by an
external oscillator with a frequency fEOSC (external con-
version clock operation), the typical differential reference
resistance is 0.60 1012/fEOSC and each ohm of source
resistance drving REF+ or REF– will result in 0.823
10–6 fEOSCppm gain error. The effect of the source
resistance on the two reference pins is additive with
respect to this gain error. The typical FS errors for various
combinations of source resistance seen by the REF+ and
REF– pins and external capacitance CREF connected to
these pins are shown in Figures 17 and 18. Typical – FS
errors are similar to + FS errors with opposite polarity.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
For LTC2411, when FO = LOW (internal oscillator and 60Hz
notch), every 100
of source resistance driving REF+ or
APPLICATIO S I FOR ATIO
WU
UU
VINCM (V)
0
OFFSET
ERROR
(ppm
OF
V
REF
)
30
–30
40
–40
50
–50
4
2411 F16
20
–20
10
–10
0
1
C
D
F
0.5
2
1.5
3
3.5
4.5
2.5
5
FO = GND
TA = 25°C
RSOURCEIN– = 500
CIN = 10F
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = IN– = VINCM
A:
RIN = +400
B:
RIN = +200
C:
RIN = +100
D:
RIN = 0
E:
RIN = –100
F:
RIN = –200
G:
RIN = –400
E
B
A
G
Figure 16. Offset Error vs Common Mode Voltage
(VINCM = IN
+ = IN–) and Input Source Resistance Imbalance
(
RIN = RSOURCEIN+ – RSOURCEIN–) for Large CIN Values (CIN ≥ 1F)
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