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參數(shù)資料
| 型號： | LTC2411-1IMS#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/DCONV DIFF INPUT&REF 10MSOP |
| 標準包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 6.8 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 1mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
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LTC2411/LTC2411-1
12
integrity of the conversion result and of the serial interface
mode selection. (See the 2-wire I/O sections in the Serial
Interface Timing Modes section.)
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 1ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2411/LTC2411-1 start a normal conversion
cycle and follow the succession of states described above.
The first conversion result following POR is accurate
within the specifications of the device if the power supply
voltage is restored within the operating range (2.7V to
5.5V) before the end of the POR time interval.
Reference Voltage Range
The LTC2411/LTC2411-1 accept a truly differential exter-
nal reference voltage. The absolute/common mode volt-
age specification for the REF+ and REF– pins covers the
entire range from GND to VCC. For correct converter
operation, the REF+ pin must always be more positive than
the REF– pin.
The LTC2411/LTC2411-1 can accept a differential refer-
ence voltage from 0.1V to VCC. The converter output noise
is determined by the thermal noise of the front-end cir-
cuits, and, as such, its value in nanovolts is nearly constant
with reference voltage. A decrease in reference voltage will
not significantly improve the converter’s effective resolu-
tion. On the other hand, a reduced reference voltage will
improve the converter’s overall INL performance. A reduced
reference voltage will also improve the converter perfor-
mance when operated with an external conversion clock
(external FOsignal)atsubstantiallyhigheroutputdatarates.
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the IN+ and IN– input pins
extending from GND – 0.3V to VCC + 0.3V. Outside
these limits, the ESD protection devices begin to turn on
and the errors due to input leakage current increase
rapidly. Within these limits, the LTC2411/LTC2411-1 con-
vert the bipolar differential input signal, VIN = IN+ – IN–,
from – FS = – 0.5 VREF to +FS = 0.5 VREF where VREF =
REF+ – REF –. Outside this range the converter indicates
the overrange or the underrange condition using distinct
output codes.
Input signals applied to IN+ and IN– pins may extend by
300mV below ground and above VCC. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN+ and IN– pins without affecting the perfor-
mance of the device. In the physical layout, it is important
to maintain the parasitic capacitance of the connection
between these series resistors and the corresponding pins
as low as possible; therefore, the resistors should be
located as close as practical to the pins. In addition, series
resistors will introduce a temperature dependent offset
error due to the input leakage current. A 1nA input leakage
current will develop a 1ppm offset error on a 5k resistor if
VREF = 5V. This error has a very strong temperature
dependency.
Output Data Format
The LTC2411/LTC2411-1 serial output data stream is 32
bits long. The first 3 bits represent status information in-
dicating the sign and conversion state. The next 24 bits are
the conversion result, MSB first. The remaining 5 bits are
sub LSBs beyond the 24-bit level that may be included in
averaging or discarded without loss of resolution. The third
and fourth bits together are also used to indicate an
underrange condition (the differential input voltage is be-
low – FS) or an overrange condition (the differential input
voltage is above + FS).
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this
bit is LOW.
Bit 28 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 29 also
provides the underrange or overrange indication. If both
Bit 29 and Bit 28 are HIGH, the differential input voltage is
APPLICATIO S I FOR ATIO
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