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參數(shù)資料
| 型號： | LTC2293CUP |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs |
| 中文描述： | DUAL 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| 封裝： | 9 X 9 MM, PLASTIC, MO-220-WNJR, QFN-64 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大?。?/td> | 1020K |
| 代理商： | LTC2293CUP |
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LTC2293/LTC2292/LTC2291
20
229321f
APPLICATIOU
W
U
U
The noise performance of the LTC2293/LTC2292/LTC2291
can depend on the clock signal quality as much as on the
analog input. Any noise present on the clock signal will
result in additional aperture jitter that will be RMS summed
with the inherent ADC aperture jitter.
In applications where jitter is critical, such as when digitiz-
ing high input frequencies, use as large an amplitude as
possible. Also, if the ADC is clocked with a sinusoidal
signal, filter the CLK signal to reduce wideband noise and
distortion products generated by the source.
It is recommended that CLKA and CLKB are shorted
together and driven by the same clock source. If a small
time delay is desired between when the two channels
sample the analog inputs, CLKA and CLKB can be driven
by two different signals. If this delay exceeds 1ns, the
performance of the part may degrade. CLKA and CLKB
should not be driven by asynchronous signals.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2293/LTC2292/
LTC2291 is 65Msps (LTC2293), 40Msps (LTC2292), and
25Msps (LTC2291). For the ADC to operate properly, the
CLK signal should have a 50% (
±
5%) duty cycle. Each half
cycle must have at least 7.3ns (LTC2293), 11.8ns
(LTC2292), and 18.9ns (LTC2291) for the ADC internal
circuitry to have enough settling time for proper operation.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The
input clock duty cycle can vary from 40% to 60% and the
clock duty cycle stabilizer will maintain a constant 50%
internal duty cycle. If the clock is turned off for a long
period of time, the duty cycle stabilizer circuit will require
a hundred clock cycles for the PLL to lock onto the input
clock. To use the clock duty cycle stabilizer, the MODE pin
should be connected to 1/3V
DD
or 2/3V
DD
using external
resistors. The MODE pin controls both Channel A and
Channel B—the duty cycle stabilizer is either on or off for
both channels.
The lower limit of the LTC2293/LTC2292/LTC2291 sample
rate is determined by droop of the sample-and-hold cir-
cuits. The pipelined architecture of this ADC relies on
storing analog signals on small valued capacitors. Junc-
tion leakage will discharge the capacitors. The specified
minimum operating frequency for the LTC2293/LTC2292/
LTC2291 is 1Msps.
DIGITAL OUTPUTS
Digital Output Buffers
Figure 12 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV
DD
and OGND, iso-
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50
to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the digi-
tal output loading can affect the performance. The digital
outputs of the LTC2293/LTC2292/LTC2291 should drive a
minimal capacitive load to avoid possible interaction
Figure 11. Sinusoidal Single-Ended CLK Drive
CLK
50
0.1
μ
F
0.1
μ
F
4.7
μ
F
1k
1k
FERRITE
BEAD
CLEAN
SUPPLY
SINUSOIDAL
CLOCK
INPUT
229321 F11
NC7SVU04
LTC2293
LTC2292
LTC2291
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2293CUP#PBF | 功能描述:IC ADC DUAL 12BIT 65MSPS 64QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| LTC2293CUP#TRPBF | 功能描述:IC ADC DUAL 12BIT 65MSPS 64QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| LTC2293IUP | 制造商:Linear Technology 功能描述:MS-ADC/High Speed, Dual 12-bit, 65Msps Low Power ADC |
| LTC2293IUP#PBF | 功能描述:IC ADC DUAL 12BIT 65MSPS 64QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| LTC2293IUP#TRPBF | 功能描述:IC ADC DUAL 12BIT 65MSPS 64QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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