參數(shù)資料
型號(hào): LTC2293CUP
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs
中文描述: DUAL 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
封裝: 9 X 9 MM, PLASTIC, MO-220-WNJR, QFN-64
文件頁(yè)數(shù): 11/28頁(yè)
文件大小: 1020K
代理商: LTC2293CUP
LTC2293/LTC2292/LTC2291
11
229321f
PIU
A
INA+
(Pin 1):
Channel A Positive Differential Analog
Input.
A
INA–
(Pin 2):
Channel A Negative Differential Analog
Input.
REFHA (Pins 3, 4):
Channel A High Reference. Short
together and bypass to Pins 5, 6 with a 0.1
μ
F ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 5, 6 with an additional 2.2
μ
F ceramic chip capacitor
and to ground with a 1
μ
F ceramic chip capacitor.
REFLA (Pins 5, 6):
Channel A Low Reference. Short
together and bypass to Pins 3, 4 with a 0.1
μ
F ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 3, 4 with an additional 2.2
μ
F ceramic chip capacitor
and to ground with a 1
μ
F ceramic chip capacitor.
V
DD
(Pins 7, 10, 18, 63):
Analog 3V Supply. Bypass to
GND with 0.1
μ
F ceramic chip capacitors.
CLKA (Pin 8):
Channel A Clock Input. The input sample
starts on the positive edge.
CLKB (Pin 9):
Channel B Clock Input. The input sample
starts on the positive edge.
REFLB (Pins 11, 12):
Channel B Low Reference. Short
together and bypass to Pins 13, 14 with a 0.1
μ
F ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 13, 14 with an additional 2.2
μ
F ceramic chip ca-
pacitor and to ground with a 1
μ
F ceramic chip capacitor.
REFHB (Pins 13, 14):
Channel B High Reference. Short
together and bypass to Pins 11, 12 with a 0.1
μ
F ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 11, 12 with an additional 2.2
μ
F ceramic chip ca-
pacitor and to ground with a 1
μ
F ceramic chip capacitor.
A
INB–
(Pin 15):
Channel B Negative Differential Analog
Input.
A
INB+
(Pin 16):
Channel B Positive Differential Analog
Input.
GND (Pins 17, 64):
ADC Power Ground.
SENSEB (Pin 19):
Channel B Reference Programming Pin.
Connecting SENSEB to V
CMB
selects the internal reference
and a
±
0.5V input range. V
DD
selects the internal reference
and a
±
1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEB selects an input
range of
±
V
SENSEB
.
±
1V is the largest valid input range.
V
CMB
(Pin 20):
Channel B 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2
μ
F ceramic chip
capacitor. Do not connect to V
CMA
.
LTC2291: I
OVDD
vs Sample Rate,
5MHz Sine Wave Input, –1dB,
O
VDD
= 1.8V
LTC2291: I
VDD
vs Sample Rate,
5MHz Sine Wave Input, –1dB
LTC2291: SFDR vs Input Level,
f
IN
= 5MHz, 2V Range, 25Msps
TYPICAL PERFOR U
SAMPLE RATE (Msps)
I
V
229321 G46
70
60
50
40
30
0
10
20
5
15
25
30
35
2V RANGE
1V RANGE
0
10
SAMPLE RATE (Msps)
20
5
15
25
30
35
I
O
229321 G47
6
4
2
0
INPUT LEVEL (dBFS)
–60
–50
– 40
–20
–30
–10
0
S
229321 G45
120
110
100
90
80
70
60
50
40
30
20
dBFS
dBc
90dBc SFDR
REFERENCE LINE
相關(guān)PDF資料
PDF描述
LTC2293IUP Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs
LTC2293UP Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs
LTC2291CUP Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs
LTC2291IUP Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs
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