AINA+ (Pin 1): Channel A Positive" />
參數(shù)資料
型號： LTC2291IUP#PBF
廠商： Linear Technology
文件頁數(shù)： 3/28頁
文件大小： 0K
描述： IC ADC DUAL 12BIT 25MSPS 64QFN
標(biāo)準(zhǔn)包裝： 40
位數(shù)： 12
采樣率（每秒）： 25M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 180mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-QFN（9x9）
包裝： 管件
輸入數(shù)目和類型： 2 個單端，雙極; 2 個差分, 雙極
產(chǎn)品目錄頁面： 1349 (CN2011-ZH PDF)
LTC2293/LTC2292/LTC2291
11
229321fa
UU
U
PI FU CTIO S
AINA+ (Pin 1): Channel A Positive Differential Analog
Input.
AINA– (Pin 2): Channel A Negative Differential Analog
Input.
REFHA (Pins 3, 4): Channel A High Reference. Short
together and bypass to Pins 5, 6 with a 0.1
F ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 5, 6 with an additional 2.2
F ceramic chip capacitor
and to ground with a 1
F ceramic chip capacitor.
REFLA (Pins 5, 6): Channel A Low Reference. Short
together and bypass to Pins 3, 4 with a 0.1
F ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 3, 4 with an additional 2.2
F ceramic chip capacitor
and to ground with a 1
F ceramic chip capacitor.
VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to
GND with 0.1
F ceramic chip capacitors.
CLKA (Pin 8): Channel A Clock Input. The input sample
starts on the positive edge.
CLKB (Pin 9): Channel B Clock Input. The input sample
starts on the positive edge.
REFLB (Pins 11, 12): Channel B Low Reference. Short
together and bypass to Pins 13, 14 with a 0.1
F ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 13, 14 with an additional 2.2
F ceramic chip ca-
pacitor and to ground with a 1
F ceramic chip capacitor.
REFHB (Pins 13, 14): Channel B High Reference. Short
together and bypass to Pins 11, 12 with a 0.1
F ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 11, 12 with an additional 2.2
F ceramic chip ca-
pacitor and to ground with a 1
F ceramic chip capacitor.
AINB– (Pin 15): Channel B Negative Differential Analog
Input.
AINB+ (Pin 16): Channel B Positive Differential Analog
Input.
GND (Pins 17, 64): ADC Power Ground.
SENSEB (Pin 19): Channel B Reference Programming Pin.
Connecting SENSEB to VCMB selects the internal reference
and a
±0.5V input range. VDD selects the internal reference
and a
±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEB selects an input
range of
±VSENSEB. ±1V is the largest valid input range.
VCMB (Pin 20): Channel B 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2
F ceramic chip
capacitor. Do not connect to VCMA.
LTC2291: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB,
OVDD = 1.8V
LTC2291: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
LTC2291: SFDR vs Input Level,
fIN = 5MHz, 2V Range, 25Msps
TYPICAL PERFOR A CE CHARACTERISTICS
UW
SAMPLE RATE (Msps)
I VDD
(mA)
229321 G46
70
60
50
40
30
0
10
20
515
25
30
35
2V RANGE
1V RANGE
0
10
20
515
25
30
35
SAMPLE RATE (Msps)
I OVDD
(mA)
229321 G47
6
4
2
0
INPUT LEVEL (dBFS)
–60
–50
– 40
–20
–30
–10
0
SFDR
(dBc
AND
dBFS)
229321 G45
120
110
100
90
80
70
60
50
40
30
20
dBFS
dBc
90dBc SFDR
REFERENCE LINE
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