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參數(shù)資料
| 型號： | LTC2274CUJ#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40 |
| 封裝： | 6 X 6 MM, PLASTIC, QFN-40 |
| 文件頁數(shù)： | 9/40頁 |
| 文件大?。?/td> | 897K |
| 代理商： | LTC2274CUJ#TR |
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LTC2274
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APPLICATIONS INFORMATION
CONVERTER OPERATION
The core of the LTC2274 is a CMOS pipelined multi-step
converter with a front-end PGA. As shown in Figure 1, the
converter has ve pipelined ADC stages. A sampled analog
input will result in a digitized value nine clock cycles later
(see the Timing Diagram section). The analog input (AIN+,
AIN–) is differential for improved common mode noise im-
munity and to maximize the input range. Additionally, the
differential input drive will reduce even order harmonics
of the sample and hold circuit. The encode clock input
(ENC+, ENC–) is also differential for improved common
mode noise immunity.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC, and an error residue amplier. The
function of each stage is to produce a digital representation
of its input voltage along with the resulting analog error
residue. The ADC of each stage provides the quantization,
and the residue is produced by taking the difference between
the input voltage and the output of the reconstruction DAC.
The residue is amplied by the residue amplier and passed
on to the next stage. The successive stages of the pipeline
operate on alternating phases of the clock so that when
odd stages are outputting their residue, the even stages
are acquiring that residue and vice versa.
The pipelined ADC of the LTC2274 has two phases of
operation determined by the state of the differential
ENC+/ENC– input pins. For brevity, the text will refer to
ENC+ greater than ENC– as ENC high and ENC+ less than
ENC– as ENC low.
When ENC is low, the analog input is sampled differentially
onto the input sample-and-hold capacitors, inside the “S/H
& PGA” block of Figure 1. On the rising edge of ENC, the
voltage on the sample capacitors is held. While ENC is
high, the held input voltage is buffered by the S/H amplier
which drives the rst pipelined ADC stage. The rst stage
acquires the output of the S/H amplier during the high
phase of ENC. On the falling edge of ENC, the rst stage
produces its residue which is acquired by the second stage.
The process continues to the end of the pipeline.
Each ADC stage following the rst has additional error
correction range to accommodate ash and amplier offset
errors. Results from all of the ADC stages are digitally
delayed such that the results can be properly combined
in the correction logic before being encoded, serialized,
and sent to the output buffer.
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| LTC2274CUJ | 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40 |
| LTC2274IUJ#TR | 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40 |
| LTC2274IUJ | 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| LTC2274CUJ-TRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 105Msps Serial Output ADC |
| LTC2274IUJ | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 105Msps Serial Output ADC |
| LTC2274IUJ#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 105Msps 16-bit Serial 40-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16-BIT 105MSPS 40-QFN 制造商:Linear Technology 功能描述:IC ADC 16BIT 105MSPS QFN-40 制造商:Linear Technology 功能描述:IC, ADC, 16BIT, 105MSPS, QFN-40; Resolution (Bits):16bit; Sampling Rate:105MSPS; Supply Voltage Type:Single; Supply Voltage Min:3.135V; Supply Voltage Max:3.465V; Supply Current:394mA; Digital IC Case Style:QFN; No. of Pins:40 ;RoHS Compliant: Yes |
| LTC2274IUJ#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 105Msps 16-bit Serial 40-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16-BIT 105MSPS 40-QFN |
| LTC2274IUJ-PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 105Msps Serial Output ADC |
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