參數(shù)資料
型號(hào)： LTC2262IUJ-14#TRPBF
廠商： LINEAR TECHNOLOGY CORP
元件分類(lèi)： ADC
英文描述： 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
封裝： 6 X 6 MM, LEAD FREE, PLASTIC, QFN-40
文件頁(yè)數(shù)： 13/28頁(yè)
文件大?。?/td> 614K
代理商： LTC2262IUJ-14#TRPBF
LTC2262-14
20
226214fa
switching of most of the bits will cause large currents in
the ground plane. By inverting every other bit, the alter-
nate bit polarity mode makes half of the bits transition
high while half of the bits transition low. To rst order,
this cancels current ow in the ground plane, reducing
the digital noise.
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11, D13.) The alternate
bit polarity mode is independent of the digital output ran-
domizer—either, both or neither function can be on at the
same time. When alternate bit polarity mode is on, the data
format is offset binary and the 2’s complement control bit
has no effect. The alternate bit polarity mode is enabled
by serially programming mode control register A4.
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D13-D0) to known values:
All 1s: All outputs are 1
All 0s: All outputs are 0
Alternating: Outputs change from all 1s to all 0s on
alternating samples
Checkerboard: Outputs change from 101010101010101
to 010101010101010 on alternating samples
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement, randomizer, alternate-bit-polarity.
Output Disable
The digital outputs may be disabled by serially program-
ming mode control register A3. All digital outputs including
OF and CLKOUT are disabled. The high impedance disabled
state is intended for long periods of inactivity—it is too
slow to multiplex a data bus between multiple converters
at full speed.
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire A/D converter is powered
down, resulting in 0.5mW power consumption. Sleep mode
is enabled by mode control register A1 (serial program-
ming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitors on VREF,
REFH, and REFL. For the suggested values in Figure 8,
the A/D will stabilize after 2ms.
In nap mode the A/D core is powered down while the
internal reference circuits stay active, allowing faster
wake-up than from sleep mode. Recovering from nap
APPLICATIONS INFORMATION
CLKOUT
OF
D13/D0
D12/D0
D2/D0
D1/D0
D0
226214 F15
OF
D13
D12
D2
D1
D0
RANDOMIZER
ON
D13
FPGA
PC BOARD
D12
D2
D1
D0
226214 F16
D0
D1/D0
D2/D0
D12/D0
D13/D0
OF
CLKOUT
LTC2262-14
Figure 15. Functional Equivalent of Digital Output Randomizer
Figure 16. Unrandomizing a Randomized Digital
Output Signal
相關(guān)PDF資料
PDF描述
LTC2262CUJ-14#PBF 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
LTC2262IUJ-12#PBF 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
LTC2262CUJ-12#TRPBF 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
LTC2262IUJ-12#TRPBF 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
LTC2262CUJ-12#PBF 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC40
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