- 您現在的位置：買賣IC網 > PDF目錄10070 > LTC2259IUJ-14#TRPBF (Linear Technology)IC ADC 14BIT 80MSPS 40-QFN PDF資料下載
參數資料
| 型號： | LTC2259IUJ-14#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數： | 18/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 80MSPS 40-QFN |
| 產品培訓模塊： | LTC2262 - Ultra Low Power High Speed ADCs |
| 標準包裝： | 2,000 |
| 位數： | 14 |
| 采樣率（每秒）： | 80M |
| 數據接口： | 并聯(lián)，串行，SPI |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 105mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 40-QFN（6x6） |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 1 個差分 |
| 配用： | DC890B-ND - BOARD USB DATA COLLECTION |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
25
226114fc
LTC2261-14
LTC2260-14/LTC2259-14
For more information www.linear.com/LTC2261-14
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11, D13.) The alter-
nate bit polarity mode is independent of the digital output
randomizer—either, both or neither function can be on
at the same time. When alternate bit polarity mode is on,
the data format is offset binary and the 2’s complement
control bit has no effect. The alternate bit polarity mode is
enabledbyseriallyprogrammingmodecontrolregisterA4.
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D13-D0) to known values:
All 1s: All outputs are 1
All 0s: All outputs are 0
Alternating: Outputs change from all 1s to all 0s on
alternating samples
Checkerboard:Outputschangefrom101010101010101
to 010101010101010 on alternating samples
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement, randomizer, alternate-bit-polarity.
Output Disable
The digital outputs may be disabled by serially program-
mingmodecontrolregisterA3.Alldigitaloutputsincluding
OFandCLKOUTaredisabled.Thehighimpedancedisabled
state is intended for long periods of inactivity—it is too
slow to multiplex a data bus between multiple converters
at full speed.
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire A/D converter is powered
down,resultingin0.5mWpowerconsumption.Sleepmode
is enabled by mode control register A1 (serial program-
ming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitors on VREF,
REFH, and REFL. For the suggested values in Figure 8,
the A/D will stabilize after 2ms.
In nap mode the A/D core is powered down while the
internal reference circuits stay active, allowing faster
wake-up than from sleep mode. Recovering from nap
mode requires at least 100 clock cycles. If the applica-
tion demands very accurate DC settling then an additional
50s should be allowed so the on-chip references can
settle from the slight temperature shift caused by the
change in supply current as the A/D leaves nap mode.
Nap mode is enabled by mode control register A1 in the
serial programming mode.
DEVICE PROGRAMMING MODES
The operating modes of the LTC2261-14 can be pro-
grammed by either a parallel interface or a simple serial
interface. The serial interface has more flexibility and
can program all available modes. The parallel interface
is more limited and can only program some of the more
commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK and SDI pins are binary logic
inputs that set certain operating modes. These pins can
be tied to VDD or ground, or driven by 1.8V, 2.5V or 3.3V
CMOS logic. Table 2 shows the modes set by CS, SCK
and SDI.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN
DESCRIPTION
CS
Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK
Digital Output Mode Control Bit
0 = Full-Rate CMOS Output Mode
1 = Double-Data Rate LVDS Output Mode
(3.5mA LVDS Current, Internal Termination Off)
SDI
Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode
applicaTions inForMaTion
相關PDF資料 |
PDF描述 |
|---|---|
| MS27466T15A35P | CONN RCPT 37POS WALL MNT W/PINS |
| VE-BN4-IV-F2 | CONVERTER MOD DC/DC 48V 150W |
| VE-BN3-IV-F4 | CONVERTER MOD DC/DC 24V 150W |
| IDT72245LB25PFI8 | IC FIFO 1024X18 SYNC 25NS 64QFP |
| MS3102E28-22SY | CONN RCPT 6POS BOX MNT W/SCKT |
相關代理商/技術參數 |
參數描述 |
|---|---|
| LTC2259IUJ-16 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 80Msps Ultralow Power 1.8V ADC |
| LTC2259IUJ-16#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 80Msps 16-bit Parallel/LVDS 40-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT 80MSPS 40QFN |
| LTC2259IUJ-16#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 80Msps 16-bit Parallel/LVDS 40-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16BIT 80MSPS 40QFN |
| LTC2259IUJ-16PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 80Msps Ultralow Power 1.8V ADC |
| LTC2259IUJ-16TRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 80Msps Ultralow Power 1.8V ADC |
發(fā)布緊急采購，3分鐘左右您將得到回復。